• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.21 no.2
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• pp.104-110
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• 2008

In this paper we proposed a new source-drain structure for N-type MOSFET which can suppress the output resistance reduction of a device in saturation region due to soft break down leakage at high drain voltage when the gate is biased around relatively low voltage. When a device is generally used as a switch at high gate bias the current level is very important for the operation. but in electronic circuit like an amplifier we should mainly consider the output resistance for the stable voltage gain and the operation at low gate bias. Hence with T-SUPREM simulator we designed devices that operate at low gate bias and high gate bias respectively without a extra photo mask layer and ion-implantation steps. As a result the soft break down leakage due to impact ionization is reduced remarkably and the output resistance increases about 3 times in the device that operates at the low gate bias. Also it is expected that electronic circuit designers can easily design a circuit using the offered N-type MOSFET device with the better output resistance.

• Journal of IKEEE
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• v.18 no.1
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• pp.37-44
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• 2014

In this paper we present an LDO based on an error amplifier. The designed error amplifier has a gain of 89.93dB at low frequencies. This amplifier's Bandwidth is 50.8MHz and its phase margin is $59.2^{\circ}C$. Also we proposed a BGR. This BGR has a low output variation with temperature and its PSRR at 1 KHz is -71.5dB. For a temperature variation from $-40^{\circ}C$ to $125^{\circ}C$ we have just 9.4mV variation in 3.3V LDO output. Also it is stable for a wide range of output load currents [0-200mA] and a $1{\mu}F$ output capacitor and its line regulation and especially load regulation is very small comparing other papers. The PSRR of proposed LDO is -61.16dB at 1 KHz. Also we designed it for several output voltages by using a ladder of resistors, transmission gates and a decoder. Low power consumption is the other superiority of this LDO which is just 1.55mW in full load. The circuit was designed in $0.35{\mu}m$ CMOS process.

• Proceedings of the KIEE Conference
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• 2006.04a
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• pp.288-290
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• 2006

An efficiency improving method for Uninterruptible Power Supply System(UPS) was developed by using OP-AMP based application circuits such as voltage detection device, current detection device and static switch control device. The efficiency improving algorithm was made by mixing the operating concepts of On-Line type UPS with the operating concepts of Off-Line type UPS. The UPS' inverter does not work if the UPS' output load current is not higher than the low load operating current which is about 0-30(%) of the UPS' output load capacity. The low load operating current is adjustable within the half of the UPS' output load capacity. If the UPS' output load current is rising over than the low load operating current, the UPS' inverter starts working and the inverter output power feeds to the loads of UPS. If UPS' input power breaks out while UPS' inverter does not operate because the load current is low, the inverter starts working within 4(ms) with excessive output voltage which is ${\pm}$8(%) of normal UPS' output voltage. Like these. UPS can continuously feeds power to it's load device and reduce power consumptions.

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.48 no.4
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• pp.461-466
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• 1999

A CMOS op amp with rail-to-rail input and output ranges is designed in a one-volt supply. The output stage of the op amp is used in a common source amplifier that operates in sub-threshold region to design a low voltage op amp with rail-to-tail output range. To drive heavy resistor and capacitor loads with rail-to-rail output ranges, a common source amplifier which has a low output resistance is utilized. A bulk-driven differential pair and a bulk-driven folded cascode amplifier are used in the designed op amp to increase input range and achieve 1 V operation. Post layout simulation results show that low frequency gain is about 58 ㏈ and gain bandwidth I MHz. The designed op amp has been fabricated in a 0.8${\mu}{\textrm}{m}$ standard CMOS process. The measured results show that this op amp provides rail-to-rail output range, 56㏈ dc gain with 1 MΩ load and has 0.4 MHz gain-bandwidth with 130 ㎊ and 1 kΩ loads.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.56 no.2
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• pp.383-388
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• 2007

This paper considers a low-order dynamic output feedback controller design problem. Since the proposed control law inherently has a low-pass filter property, it can alleviate the mal-effects of the sensor noise without additional filter designs. Frequency domain analysis shows the characteristics of the proposed control law against measurement noise. The effectiveness of the proposed control law is illustrated by numerical simulations with a rotary inverted pendulum and a convey-crane. Using only one integrator the proposed control law has the advantage to the stabilization problem with sensor noise as well as it can successfully replace the measurements of derivative terms in a state feedback control law.

• Journal of Electrical Engineering and Technology
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• v.10 no.1
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• pp.216-226
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• 2015

The neutral beam injection generate ultra-high temperature energy in the tokamak of nuclear fusion. The neutral beam injection make up arc power supply, filament power supply and acceleration & deceleration power supply. The arc power supply has characteristics of low voltage and high current. Arc power supply generate arc through constant output of voltage and current. So this paper proposed suitable buck converter for low voltage and high current. The proposed buck converter used parallel switch because it can be increased capacity and decrease conduction loss. When an arc generated, the neutral beam injection chamber occur high voltage. And it will break output capacitor of buck converter. Therefore the output capacitor was removed in the proposed converter. Thus the proposed converter should be designed for the characteristics of low voltage and high current. Also, the arc power supply should be guaranteed for system stability. The proposed parallel buck converter enables the system stability of the divided low output voltage and high current. The proposed converter with constant output be the most important design of the output inductor. In this paper, designed arc power supply verified operation of system and stability through simulation and prototype. After it is applied to the 288[kW] arc power supply for neutral beam injection.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.11
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• pp.34-40
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• 2011

This paper presents a low-dropout (LDO) linear regulator using ultra-low output impedance buffer for frequency compensation. The proposed buffer achieves ultra low output impedance with dual shunt feedback loops, which makes it possible to improve load and line regulations as well as frequency compensation for low voltage applications. A reference control scheme for programmable output voltage of the LDO linear regulator is presented. The designed LDO linear regulator works under the input voltage of 2.5~4.5V and provides up to 300mA load current for an output voltage range of 0.6~3.3V.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.56 no.5
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• pp.892-897
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• 2007

This paper presents the output filter design and the output characteristic analysis by cut-off frequency set up of the LCR filter on NPC multi-level inverter with trap-filter. The single-phase NPC three-level inverter operates at low switching frequency. The proposed LC trap filter is comprised of a conventional LCR output filter, by using LC trap filter the need for high damping resistor and low LC cut-off frequency is eliminated. Also. low damping resistor is increased the output filter system. The multilevel inverter system used NPC type inverter in proper system for high power application and controller is used DSP(TMS320C31). The effectiveness of proposed system confirmed the validity through SPICE simulation and experimental results.

• Proceedings of the KIEE Conference
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• 2001.10a
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• pp.215-218
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• 2001

In conventional three-phase rectifiers, it was necessary to use a transformer to obtain low output voltage. In this paper, we propose a new three-phase rectifiers circuit that achieves low voltage by using a very simple circuit configuration that does not have a transformer and does not need any complex control. We also describe the operation principle of the proposed circuit, and derive a theoretical formula for its current waveform. On the basis of this formula it also explores the theoretical input/output current characteristics, theoretical current amplification factor, and theoretical output voltage characteristics of these theoretical values with experimentally obtained input/output current characteristics, current amplification factor, and output voltage characteristics, allowed us to confirm the soundness of our theoretical analyses.

• Journal of Power Electronics
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• v.16 no.1
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• pp.1-8
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• 2016

Dead time is typically incorporated in voltage source inverter systems to prevent short circuit cases. However, dead time causes an error between the output voltage and reference voltage. Hence, voltage equation-based algorithms, such as motor parameter estimation and back electromotive force (EMF)-based sensorless algorithms, are prone to estimation errors. Several dead-time compensation methods have been developed to reduce output voltage errors. However, voltage errors are still common in zero current crossing areas, and an effect of the error is much worse in a low speed region. Therefore, employing voltage equation-based algorithms in low speed regions is difficult. This study analyzes the conventional dead-time compensation method and output voltage errors in low speed operation areas. A current shaping method that can reduce output voltage errors is also proposed. Experimental results prove that the proposed method reduces voltage errors and improves the accuracy of the parameter estimation method and the performance of the back EMF-based sensorless algorithm.