• Title/Summary/Keyword: low latency

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Reducing latency of neural automatic piano transcription models (인공신경망 기반 저지연 피아노 채보 모델)

  • Dasol Lee;Dasaem Jeong
    • The Journal of the Acoustical Society of Korea
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    • v.42 no.2
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    • pp.102-111
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    • 2023
  • Automatic Music Transcription (AMT) is a task that detects and recognizes musical note events from a given audio recording. In this paper, we focus on reducing the latency of real-time AMT systems on piano music. Although neural AMT models have been adapted for real-time piano transcription, they suffer from high latency, which hinders their usefulness in interactive scenarios. To tackle this issue, we explore several techniques for reducing the intrinsic latency of a neural network for piano transcription, including reducing window and hop sizes of Fast Fourier Transformation (FFT), modifying convolutional layer's kernel size, and shifting the label in the time-axis to train the model to predict onset earlier. Our experiments demonstrate that combining these approaches can lower latency while maintaining high transcription accuracy. Specifically, our modified model achieved note F1 scores of 92.67 % and 90.51 % with latencies of 96 ms and 64 ms, respectively, compared to the baseline model's note F1 score of 93.43 % with a latency of 160 ms. This methodology has potential for training AMT models for various interactive scenarios, including providing real-time feedback for piano education.

Effects of Low Power Laser on Pain Response and Axonal Regeneration in Rat Models with Sciatic Nerve Crush Injury

  • Lee, Hong-Gyun;Kim, Yong-Eok;Min, Kyung-Ok;Yoo, Young-Dae;Kim, Kyung-Yoon;Kim, Gye-Yeop
    • Journal of International Academy of Physical Therapy Research
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    • v.3 no.1
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    • pp.345-355
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    • 2012
  • This study purposed to examine the effect of low power laser on pain response and axonal regeneration. In order to prepare peripheral nerve injury models, we crushed the sciatic nerve of Sprague-Dawley rats and treated them with low power laser for 21 days. The rats were divided into 4 groups: normal group(n=10); control group(n=10) without any treatment after the induction of sciatic nerve crush injury; experimental group I(n=10) treated with low power laser(0.21$mJ/mm^2$) after the induction of sciatic nerve crush injury; and experimental group II(n=10) treated with low power laser(5.25$mJ/mm^2$) after the induction of sciatic nerve crush injury. We measured spontaneous pain behavior(paw withdrawal latency test) and mechanical allodynia(von Frey filament test) for evaluating pain behavioral response, and measured the sciatic function index for evaluating the functional recovery of peripheral nerve before the induction of sciatic nerve crush injury and on day 1, 7, 14 and 21 after the induction. After the experiment was completed, changes in the H & E stain and toluidine blue stain were examined histopathologically, and changes in MAG(myelin associated glycoprotein) and c-fos were examined immunohistologically. According to the results of this study, when low power laser was applied to rat models with sciatic nerve crush injury for 21 days and the results were examined through pain behavior evaluation and neurobehavioral, histopathological and immunohistological analyses, low power laser was found to affect pain response and axonal regeneration in both experimental group I and experimental group II. Moreover, the effect on pain response and axonal regeneration was more positive in experimental group I to which output 0.21$mJ/mm^2$ was applied than in experimental group II to which 5.25$mJ/mm^2$ was applied.

TASL: A Traffic-Adapted Sleep/Listening MAC Protocol for Wireless Sensor Network

  • Yang, Yuan;Zhen, Fu;Lee, Tae-Seok;Park, Myong-Soon
    • Journal of Information Processing Systems
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    • v.2 no.1
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    • pp.39-43
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    • 2006
  • In this paper, we proposed TASL-MAC, a medium-access control (MAC) protocol for wireless sensor networks. In wireless sensor networks, sensor nodes are usually deployed in a special environment, are assigned with long-term work, and are supported by a limited battery. As such, reducing the energy consumption becomes the primary concern with regard to wireless sensor networks. At the same time, reducing the latency in multi-hop data transmission is also very important. In the existing research, sensor nodes are expected to be switched to the sleep mode in order to reduce energy consumption. However, the existing proposals tended to assign the sensors with a fixed Sleep/Listening schedule, which causes unnecessary idle listening problems and conspicuous transmission latency due to the diversity of the traffic-load in the network. TASL-MAC is designed to dynamically adjust the duty listening time based on traffic load. This protocol enables the node with a proper data transfer rate to satisfy the application's requirements. Meanwhile, it can lead to much greater power efficiency by prolonging the nodes' sleeping time when the traffic. We evaluate our implementation of TASL-MAC in NS-2. The evaluation result indicates that our proposal could explicitly reduce packet delivery latency, and that it could also significantly prolong the lifetime of the entire network when traffic is low.

Power Consumption Analysis by Adjusting of Check Interval in Asynchronous Wireless Sensor Network (비동기 무선센서네트워크에서 체크인터벌 조절에 따른 전력소모 분석)

  • Kim, Dongwon
    • The Journal of the Institute of Internet, Broadcasting and Communication
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    • v.19 no.3
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    • pp.91-96
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    • 2019
  • There are so many low power MAC protocols for wireless sensor network. IEEE802.15.4 among them has disadvantage of a large power consumption for synchronization. To save power consumption it use the superframe operation alternating sleep mode and awake mode. But latency is longer result from superframe operation. Typical asynchronous B-MAC can have shorter latency according to check interval. But transmitter consumes more power because of long preamble. And receiver is suffering from overhearing. In this paper, we propose the adaptive check interval scheme of B-MAC for enhancing the power consumption and delay latency performance. Its power consumption is evaluated by comparing the proposed scheme with a typical IEEE802.15.4.

Hybrid Hierarchical Architecture for Mobility Management in Mobile Content Centric Networking (이동 콘텐트 중심 네트워킹 구조에서의 하이브리드 계층적 이동성 관리 방안)

  • Lee, Ji-hoon
    • Journal of IKEEE
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    • v.22 no.4
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    • pp.1147-1151
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    • 2018
  • As personal users create and share lots of contents at any time and any places, new networking architecture such as content centric networking (CCN) has emerged. CCN utilizes content name as a packet identifier, not address. However, current CCN has a limitation for content source mobility management. The movement of content sources cause long delivery latency and long service disruption. To solve that, a hierarchical mobility management was was proposed. However, the hierarchical mobility management scheme has still the loss of interest packets and long handoff latency. So, this paper presents the hybrid hierarchical mobility management in mobile CCN environements to reduce both the loss rate of interest packets and the handoff latency. It is shown from the performance evaluations shows that the proposed scheme provides low loss rate of control message.

Gen-Z memory pool system implementation and performance measurement

  • Kwon, Won-ok;Sok, Song-Woo;Park, Chan-ho;Oh, Myeong-Hoon;Hong, Seokbin
    • ETRI Journal
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    • v.44 no.3
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    • pp.450-461
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    • 2022
  • The Gen-Z protocol is a memory semantic protocol between the memory and CPU used in computer architectures with large memory pools. This study presents the implementation of the Gen-Z hardware system configured using Gen-Z specification 1.0 and reports its performance. A hardware prototype of a DDR4 Gen-Z memory pool with an optimized character, a block device driver, and a file system for the Gen-Z hardware was designed. The Gen-Z IP was targeted to the FPGA, and a 512 GB Gen-Z memory pool was configured on an ×86 server. In the experiments, the latency and throughput of the Gen-Z memory were measured and compared with those of the local memory, SATA SSD, and NVMe using character or block device interfaces. The Gen-Z hardware exhibited superior throughput and latency performance compared with SATA SSD and NVMe at block sizes under 4 kB. The MySQL and File IO benchmark of Gen-Z showed good write performance in all block sizes and threads. Besides, it showed low latency in RocksDB's fillseq dbbench using the ext4 direct access filesystem.

Precision Assessment of Near Real Time Precise Orbit Determination for Low Earth Orbiter

  • Choi, Jong-Yeoun;Lee, Sang-Jeong
    • Journal of Astronomy and Space Sciences
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    • v.28 no.1
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    • pp.55-62
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    • 2011
  • The precise orbit determination (POD) of low earth orbiter (LEO) has complied with its required positioning accuracy by the double-differencing of observations between International GNSS Service (IGS) and LEO to eliminate the common clock error of the global positioning system (GPS) satellites and receiver. Using this method, we also have achieved the 1 m positioning accuracy of Korea Multi-Purpose Satellite (KOMPSAT)-2. However double-differencing POD has huge load of processing the global network of lots of ground stations because LEO turns around the Earth with rapid velocity. And both the centimeter accuracy and the near real time (NRT) processing have been needed in the LEO POD applications--atmospheric sounding or urgent image processing--as well as the surveying. An alternative to differential GPS for high accuracy NRT POD is precise point positioning (PPP) to use measurements from one satellite receiver only, to replace the broadcast navigation message with precise post processed values from IGS, and to have phase measurements of dual frequency GPS receiver. PPP can obtain positioning accuracy comparable to that of differential positioning. KOMPSAT-5 has a precise dual frequency GPS flight receiver (integrated GPS and occultation receiver, IGOR) to satisfy the accuracy requirements of 20 cm positioning accuracy for highly precise synthetic aperture radar image processing and to collect GPS radio occultation measurements for atmospheric sounding. In this paper we obtained about 3-5 cm positioning accuracies using the real GPS data of the Gravity Recover and Climate Experiment (GRACE) satellites loaded the Blackjack receiver, a predecessor of IGOR. And it is important to reduce the latency of orbit determination processing in the NRT POD. This latency is determined as the volume of GPS measurements. Thus changing the sampling intervals, we show their latency to able to reduce without the precision degradation as the assessment of their precision.

MDA-SMAC: An Energy-Efficient Improved SMAC Protocol for Wireless Sensor Networks

  • Xu, Donghong;Wang, Ke
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • v.12 no.10
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    • pp.4754-4773
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    • 2018
  • In sensor medium access control (SMAC) protocol, sensor nodes can only access the channel in the scheduling and listening period. However, this fixed working method may generate data latency and high conflict. To solve those problems, scheduling duty in the original SMAC protocol is divided into multiple small scheduling duties (micro duty MD). By applying different micro-dispersed contention channel, sensor nodes can reduce the collision probability of the data and thereby save energy. Based on the given micro-duty, this paper presents an adaptive duty cycle (DC) and back-off algorithm, aiming at detecting the fixed duty cycle in SMAC protocol. According to the given buffer queue length, sensor nodes dynamically change the duty cycle. In the context of low duty cycle and low flow, fair binary exponential back-off (F-BEB) algorithm is applied to reduce data latency. In the context of high duty cycle and high flow, capture avoidance binary exponential back-off (CA-BEB) algorithm is used to further reduce the conflict probability for saving energy consumption. Based on the above two contexts, we propose an improved SMAC protocol, micro duty adaptive SMAC protocol (MDA-SMAC). Comparing the performance between MDA-SMAC protocol and SMAC protocol on the NS-2 simulation platform, the results show that, MDA-SMAC protocol performs better in terms of energy consumption, latency and effective throughput than SMAC protocol, especially in the condition of more crowded network traffic and more sensor nodes.

High-Speed Reed-Solomon Decoder Using New Degree Computationless Modified Euclid´s Algorithm (새로운 DCME 알고리즘을 사용한 고속 Reed-Solomon 복호기)

  • 백재현;선우명훈
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.40 no.6
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    • pp.459-468
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    • 2003
  • This paper proposes a novel low-cost and high-speed Reed-Solomon (RS) decoder based on a new degree computationless modified Euclid´s (DCME) algorithm. This architecture has quite low hardware complexity compared with conventional modified Euclid´s (ME) architectures, since it can remove completely the degree computation and comparison circuits. The architecture employing a systolic away requires only the latency of 2t clock cycles to solve the key equation without initial latency. In addition, the DCME architecture using 3t+2 basic cells has regularity and scalability since it uses only one processing element. The RS decoder has been synthesized using the 0.25${\mu}{\textrm}{m}$. Faraday CMOS standard cell library and operates at 200MHz and its data rate suppots up to 1.6Gbps. For tile (255, 239, 8) RS code, the gate counts of the DCME architecture and the whole RS decoder excluding FIFO memory are only 21,760 and 42,213, respectively. The proposed RS decoder can reduce the total fate count at least 23% and the total latency at least 10% compared with conventional ME architectures.

A Low-Complexity Processor for Joint QR decomposition and Lattice Reduction for MIMO Systems (다중 입력 다중 출력 통신 시스템을 위한 저 복잡도의 Joint QR decomposition-Lattice Reduction 프로세서)

  • Park, Min-Woo;Lee, Sang-Woo;Kim, Tae-Hwan
    • Journal of the Institute of Electronics and Information Engineers
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    • v.52 no.8
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    • pp.40-48
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    • 2015
  • This paper presents a processor that performs QR decomposition (QRD) as well as Lattice Reduction (LR) for multiple-input multiple-output (MIMO) systems. By sharing the operations commonly required in QRD and LR, the hardware complexity of the proposed processor is reduced significantly. In addition, the proposed processor is designed based on a multi-cycle architecture so as to reduce the hardware complexity. The proposed processor is implemented with 139k logic gates in a $0.18-{\mu}m$ CMOS process, and its latency is $5{\mu}s$ for $8{\times}8$ MIMO preprocessing both QRD and LR where the operating frequency is 117MHz.