• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.10a
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• pp.357-360
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• 2013

A 1.8V 2-Gb/s scalable low voltage signaling (SLVS) transmitter (TX) is designed for mobile applications requiring high speed and low power consumption. It consists of 4-lane TX for data transmission, 1-lane TX for a source synchronous clocking, and a 8-phase clock generator. The proposed SLVS TX has the scaling voltage swing from 50 mV to 650 mV and supports a high speed (HS) mode and a low power (LP) mode. An output impedance calibration scheme for the SVLS TX is proposed to improve the signal integrity. The proposed SLVS TX is implemented by using a $0.18-{\mu}m$ 1-poly 6-metal CMOS with a 1.8V supply. The simulated data jitter of the implemented SLVS TX is about 8.04 ps at the data rate of 2-Gbps. The area and power consumption of the 1-lane of the proposed SLVS TX are $422{\times}474{\mu}m^2$ and 5.35 mW/Gb/s, respectively.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.58 no.6
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• pp.1157-1165
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• 2009

In AC-PDP, it is necessary to achieve high luminance efficiency, high luminance and high definition by adopting technologies such as high xenon concentration, MgO doping, and long gap. However, it is very difficult to apply above technologies because they make the driving voltage margin reduced. Especially, high Xe concentration technology for high efficacy makes not only the driving voltage margin reduced but also the stability of reset discharge decreased at low temperature. In this paper, we studied temperature and voltage dependent stability of reset discharge and present the experimental results of the discharge characteristics at low temperature. In addition, we suggested the mechanism of bright noise and black noise at low temperature. Finally, we proposed double reset waveform to improve the bright noise and descending scan time method to improve the black noise.

• Proceedings of the KIEE Conference
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• 1999.11c
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• pp.742-744
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• 1999

In this paper, a new precharge type PFD for fast locking time of PLL is suggested. It is realized by inserting NMOS transistor and inverter into the precharge part of PFD for isolating the reset of the Up signal from the feedback signal. The new precharge type PFD generates the Up signal while the feedback signal is fixed at a high level. Therefore the new PFD output is increased than the conventional precharge type PFD output. As a result of the increased PFD output, fast locking of PLLs is achieved. Additionally, with control the falling time of the inverter, the dead-zone is reduced and the jitter characteristics are improved. The whole characteristics of PFD and PLL are simulated by using HSPICE. Simulation results show that the dead-zone is 20ps and the locking time of PLL using the new PFD is 38ns at the 350MHz frequency of referecne signal. This value is quite small compared with conventional PFD.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.05a
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• pp.773-774
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• 2015

Motion capture tracks the movement of the actor and quickly transfers it as a motion data for animation purposes. The data from the motion capture can be easily controled and applied to animating characters to make realistic movement. But conventional motion capture system is very expensive and need spacious room for its own. Recently Kinect based motion capture is widely used for its simplicity and comparably low budget. However, the Kinect based motion capture data is often corrupted by jitter and unstable data. In this paper, we propose the novel post processing method to stabilize the unwanted jitter in the motion capture data.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.10
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• pp.1-11
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• 1996

In this paper, we evaluate the performance of DD-bardner (decision-directed gardner) algorithm. We derive an analytic gain of the thiming detector that is a function of SNR and an excess bandwidth, and verify the result by simulation. We also compare the DD-gardner algorithm with the bardner algorithm with respect to tracking performance and jitter performance under low SNR and a residual frequency component.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.281-284
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• 2001

This paper describes an analog multi-phase delay-locked loop (DLL) to solve the harmonic lock problem using current-starved inverter and shunt-capacitor delay cell. The DLL can be used not only as an internal clock buffer of microprocessors and memory It's but also as a multi-phase clock generator for gigabit serial interfaces. The proposed circuit was simulated in a 0.25${\mu}{\textrm}{m}$ CMOS technology to solve harmonic lock problem and to realize fast lock-on time and low-jitter we verified time interval less than 40 ps as the simulation results.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.277-280
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• 2001

The proposed clock generator lowers the operating frequency in a system core though it keeps data bandwidth high because it has a multiphase clocking architecture. Moreover. it has a dual loop which is comprised of an inner analog phase generation loop and outer digital phase control loop. It has both advantages of DLL's wide operating range and DLL's low jitter The proposed design has been demonstrated in terms of the concept and Hspice simulation. All circuits were designed using a 0.25${\mu}{\textrm}{m}$ CMOS process and simulated with 2.5 V power supply.

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 1986.04a
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• pp.14-17
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• 1986

In this paper, it is studied on the properties of the transmission signal for being tolerant to the timing jitter at the receiver, when an ideal low pass filter is used as the pulse shaper. A model for the transmission system with minimum bandwidth is presented and the related parameters to the tolerance or stability are explained. It has been proven that the necessary condition for a stable signaling is the same as the sufficient one.

• Proceedings of the IEEK Conference
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• 2002.07b
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• pp.852-855
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• 2002

This paper presents a design of FIR near-equiripple Nyquist filters having zero-intersymbol interference (ISI) and low sensitivity to timing jitter, with coefficients taking only discrete values. Using an affine scaling linear programming algorithm, an optimum discrete coefficient set can be obtained in a feasible computational time. Also presented is a pipelined multiplier-free FIR filter realization with periodically time-varying (PTV) coefficients based on a hybrid form suitable for Nyquist filter. The realization exploits the coefficient symmetry to reduce the hardware by about one half. High speed computation and low power consumption are achieved by its pipelined and low fan-out structure.

• Transactions of the Society of Information Storage Systems
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• v.1 no.1
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• pp.48-52
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• 2005

The research topic of super-RENS technology is shifting from the signal intensity (CNR; Carrier to Noise Ratio) to the signal uniformity (Jitter or bER). To achieve an uniform signal characteristics, it is important to reduce signal fluctuation in a super-RENS disc. In this study, we investigated the relation between signal fluctuation and low frequency noise (LFN), and analyzed LFN increase in recording and readout processes. It was found that signal fluctuation had a close relationship with the LFN. Also, it was found that the recorded mark shape such a bubble type and high readout power increased the LFN in recording and readout process of a super-RENS disc. So, using non-bubble type recording material and low super-resolution readout material, we markedly improved the LFN in a super-RENS disc.