• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2007년도 하계학술대회 논문집 Vol.8
• /
• pp.111-111
• /
• 2007

Further scaling the semiconductor devices down to low dozens of nanometer needs the extremely shallow depth in junction and the intentional counter-doping in the silicon gate. Conventional ion beam ion implantation has some disadvantages and limitations for the future applications. In order to solve them, therefore, plasma source ion implantation technique has been considered as a promising new method for the high throughputs at low energy and the fabrication of the ultra-shallow junctions. In this paper, we study about the effects of DC bias and base pressure as a process parameter. The diluted mixture gas (5% $PH_3/H_2$) was used as a precursor source and chamber is used for vacuum pressure conditions. After ion doping into the Si wafer(100), the samples were annealed via rapid thermal annealing, of which annealed temperature ranges above the $950^{\circ}C$. The junction depth, calculated at dose level of $1{\times}10^{18}/cm^3$, was measured by secondary ion mass spectroscopy(SIMS) and sheet resistance by contact and non-contact mode. Surface morphology of samples was analyzed by scanning electron microscopy. As a result, we could accomplish the process conditions better than in advance.

• 한국전기전자재료학회논문지
• /
• 제24권3호
• /
• pp.240-244
• /
• 2011

The high cost of crystalline silicon solar cells has been considered as one of the major obstacles to their terrestrial applications. Spin on doping (SOD) is presented as a useful process for the manufacturing of low cost solar cells. Phosphorus (P509) was used as an n-type emitters of solar cells. N-type emitters were formed on p-type EFG ribbon Si wafers by using a SOD at different spin speed (1,000~4,000 rpm), diffusion temperatures ($800^{\circ}C{\sim}950^{\circ}C$), and diffusion time (5~30 min) in $N_2+O_2$ atmosphere. With optimum condition, we were able to achieve cell efficiency of 14.1%.

• 신재생에너지
• /
• 제18권1호
• /
• pp.29-34
• /
• 2022

The most prevalent cause of solar cell efficiency loss is reduced recombination at the metal electrode and silicon junction. To boost efficiency, a a SiO_X/poly-Si passivating interface is being developed. Poly-Si for passivating contact is formed by various deposition methods (sputtering, PECVD, LPCVD, HWCVD) where the ploy-Si characterization depends on the deposition method. The sputtering process forms a dense Si film at a low deposition rate of 2.6 nm/min and develops a low passivation characteristic of 690 mV. The PECVD process offers a deposition rate of 28 nm/min with satisfactory passivation characteristics. The LPCVD process is the slowest with a deposition rate of 1.4 nm/min, and can prevent blistering if deposited at high temperatures. The HWCVD process has the fastest deposition rate at 150 nm/min with excellent passivation characteristics. However, the uniformity of the deposited film decreases as the area increases. Also, the best passivation characteristics are obtained at high doping. Thus, it is necessary to optimize the doping process depending on the deposition method.

• KEPCO Journal on Electric Power and Energy
• /
• 제5권3호
• /
• pp.209-213
• /
• 2019

최근 전력 계통에 사용되는 주파수 조정용(F/R) 에너지 저장장치에 대하여 높은 에너지 밀도와 장수명의 안정성에 대한 요구가 증대되고 있다. 이와 관련하여 슈퍼커패시터는 장수명과 급속 충방전 특성이 우수하므로 이러한 F/R 적용을 위한 에너지 저장장치로 적합하게 여겨지고 있다. 슈퍼커패시터는 단주기 F/R 영역의 보완 운전을 담당하고 전력계통에 설치된 ESS의 장주기 운영 수명을 연장함으로써 기존 용량을 담당하는 리튬 배터리의 설치 규모와 양을 획기적으로 줄일 수 있다. 하지만 낮은 에너지 밀도는 전력 계통과 같은 큰 시스템에서 적용에 한계가 있으며 여전히 배터리를 대체할 수 있는 높은 에너지 밀도 요구에 어려움을 겪고 있다. 그러나 최근에는 리튬이온 커패시터(Lithium ion capacitor; LIC) 구조가 3.8 V 이상의 전압 구간을 구현할 수 있기 때문에 전기이중층 커패시터(Electric double layer capacitor; EDLC) 구조보다 고에너지 밀도 구현을 위한 구조로 각광을 받고 있지만 여전히 상용화를 위해서는 여러가지 전기화학적 성능에 대한 구체적인 검증 및 개발이 필요한 실정이다. 본 연구에서는 LIC의 에너지 밀도와 관계되는 용량을 증대하기 위하여 새로운 전극사전-도핑 방법을 설계하였다. 양극 활물질은 0.1% 이하의 상대습도 분위기 드라이룸에서 기계적 강도와 음극 도핑을 안정되게 수행될 수 있도록 $100{\mu}m$의 두께로 제작되었다. 또한 접촉 저항을 최소화하기 위하여 제조된 전극은 상온에서 $65^{\circ}C$까지 열 압축공정을 실시하였다. 최종적으로 LIC 구조에 대한 다양한 사전-도핑법을 설계하고 그 메커니즘을 분석하여 용량과 전기화학적 안정성이 향상된 새로운 LIC 사전-도핑 방법을 제안하였다.

• 공업화학
• /
• 제26권3호
• /
• pp.275-279
• /
• 2015

전도성 고분자인 poly(3,4-ethylenedioxythiophene) : poly(styrenesulfonate) (PEDOT : PSS)는 우수한 전기 전도도와 광투과도, 유연성을 가지고 있기 때문에 유기태양전지와 유기발광소자의 투명전극으로서 많은 각광을 받고 있다. PEDOT : PSS의 전기 전도도는 솔벤트를 도핑함에 따라 큰 폭으로 증가한다는 사실은 잘 알려져 있다. 본 연구에서는 다양한 솔벤트의 도핑과 솔벤트 후처리 공정에 따른 PEDOT : PSS 박막의 전기 전도도와 구조적 특성 변화를 연구하였다. 솔벤트 도핑으로 PEDOT : PSS의 전도도는 884 S/cm까지 증가하였고, 후처리 공정을 통해서 1131 S/cm의 전도도 값을 얻을 수 있었다. 이러한 전도도의 증가는 PSS 물질이 빠져나가거나 구조적인 재배열에 따른 전도성 PEDOT 입자의 접촉 면적이 증가함에 따른 것으로 사료되고, 광학적인 방법으로 PSS의 추출을 관찰하였다. 솔벤트 후처리 공정은 PEDOT : PSS 박막의 전도도를 향상하는 매우 효과적인 방법으로 확인되었고, 저가형 플렉서블 유기전자소자의 투명전극으로써의 사용이 적합할 것으로 예상된다.

• ETRI Journal
• /
• 제36권5호
• /
• pp.829-834
• /
• 2014

In this paper, a lateral power metal-oxide-semiconductor field-effect transistor with ultra-low specific on-resistance is proposed to be applied to a high-voltage (up to 200 V) integrated chip. The proposed structure has two characteristics. Firstly, a high level of drift doping concentration can be kept because a tilt-implanted p-drift layer assists in the full depletion of the n-drift region. Secondly, charge imbalance is avoided by an extended trench gate, which suppresses the trench corner effect occurring in the n-drift region and helps achieve a high breakdown voltage (BV). Compared to a conventional trench gate, the simulation result shows a 37.5% decrease in $R_{on.sp}$ and a 16% improvement in BV.

• Transactions on Electrical and Electronic Materials
• /
• 제13권2호
• /
• pp.69-72
• /
• 2012

In this study, deposition of low-dielectric constant SiOC(H) films by conventional plasma-enhanced chemical vapor deposition (PECVD) were investigated through various characterization techniques. The results show that, with an increase in the plasma power density, the relative dielectric constant (k) of the deposited films decreases whereas the refractive index increases. This is mainly due to the incorporation of organic molecules with $CH_3$ group into the Si-O-Si cage structure. It is as confirmed by FT-IR measurements in which the absorption peak at 1,129 $cm^{-1}$ corresponding to Si-O-Si cage structure increases with power plasma density. Electrical characterization reveals that even after fast thermal annealing process, the leakage current density of the deposited films is in the order of $10^{-11}$ A/cm at 1.5 MV/cm. The reliability of the SiOC(H) film is also further characterized by using BTS test.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2009년도 추계학술대회 논문집
• /
• pp.160-160
• /
• 2009

In recent years, the merging of nanomaterials and nano-technology into electro-optic (EO) device technology such as liquid crystal displays (LCDs) has attracted much attention because of their unique electro- and magneto-optic properties and novel display applications. One example of hybrid LC-inorganic systems is semiconductor nanorods added to LC for their strong reorientation effect and tunable refractive index. Doping of nanoparticles in LC or polymers can lead to changes in performance characteristics such as electro-optical, dielectric, memory effect, phase behavior, etc. Due to the tunability of LCDs with mixed inorganic materials, low voltage operation of a LC system can also be achieved using the significant electro-optical effect achieved through suspension of ferroelectric nanoparticles in NLC.

• 한국신재생에너지학회:학술대회논문집
• /
• 한국신재생에너지학회 2009년도 춘계학술대회 논문집
• /
• pp.111-113
• /
• 2009

This paper shows that you can achieve high quality N+ emitter layers using a screen printable phosphorous diffusion paste and firing in an infrared belt furnace. Spreading resistance measurement from a beveled sample is used to measure carrier concentration as a function of depth for different phosphorous concentrations. Contours of estimated sheet resistance are shown for different processing conditions. This paper describes newly developed low cost phosphorous pastes. It shows the characterization of the newly developed phosphorous paste (DP99-038). This low cost pastes can easily be printed and make 16% efficiency.

• 한국전기전자재료학회논문지
• /
• 제15권3호
• /
• pp.214-219
• /
• 2002

In order to elucidate the crystallographic orientation dependence of electrical properties of carbon (C)-doped GaAs epilayers, C incorporation into GaAs epilayers on high-index GaAs substrates with various crystallographic orientations from (100) to (111)A has been performed by a low pressure metalorganic chemical vapor deposition using C tetrabromide ($CBt_4$) as a C source. The hole concentration of C-doped GaAs epilayers rapidly decreases with a hump at (311)A with increasing the offset angle. Although the growth temperature and the V/III ratio are varied, the crystallographic orientation dependence of hole concentration show a same trend. The above behaviors indicate that the bonding strength of As sites on a glowing surface plays an important role in the C incorporation into the high-index GaAs substrates.