• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2022.06a
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• pp.1249-1252
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• 2022

In this paper, we propose a conceptual framework that identifies video frames in motion containing the movement of people and vehicles in traffic videos. The automatic selection of video frames in motion is an important topic in security and surveillance video because the number of videos to be monitored simultaneously is simply too large due to limited human resources. The conventional method to identify the areas in motion is to compute the differences over consecutive video frames, which has been costly because of its high computational complexity. In this paper, we reduced the overall complexity by examining only the keyframes (or I-frames). The basic assumption is that the time period between I-frames is rather shorter (e.g., 1/10 ~ 3 secs) than the usual length of objects in motion in video (i.e., pedestrian walking, automobile passing, etc.). The proposed method estimates the possibility of videos containing motion between I-frames by evaluating the difference of consecutive I-frames with the long-time statistics of the previously decoded I-frames of the same video. The experimental results showed that the proposed method showed more than 80% accuracy in short surveillance videos obtained from different locations while keeping the computational complexity as low as 20 % compared to the HM decoder.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.9C
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• pp.683-690
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• 2008

By using inherent stopping criteria of LDPC codes, the average number of iterations can be substantially reduced at high signal to noise ratio (SNR). However, we encounter a problem when hybrid automatic repeat request (H-ARQ) systems are applied. Frequent failures of decoding at low SNR region imply that the decoder leaches the maximum number of iterations frequently and thus the decoding complexity increases. In this paper, we propose a combination of stopping criteria using the syndrome weight of tentative codeword. By numerical analysis, it is shown that the decoding complexity of given H-ARQ system is reduced by 70-80% with the proposed algorithms.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.12
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• pp.2791-2797
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• 2010

In recent years, the goal of providing high speed wireless data services has generated a great amount of interest among the research community. Several researchers have shown that the capacity of the system, in the presence of flat Rayleigh fading, improves significantly with the use of combined MIMO and LDPC. To feed the soft values to LDPC decoder, the soft values must be calculated from multiple transmitter and receiver antennas in Rayleigh fading channel. It requires high computational complexity to get the soft symbols by increasing number of transmitter and receiver antennas. Therefore, this thesis proposed on effective algorithm for calculation of soft values from multiple antennas based on LLR. As result, This thesis shows that maximum 61% of computational complexity is reduced with a little loss of performance.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.12C
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• pp.1222-1230
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• 2005

We aim at increasing the throughput of the hybrid automatic retransmission request (HARQ) protocol in Space-Time (ST) coded multi-antenna transmission systems. By utilizing reliability information at the decoder, we obtain an improved probability of successful decoding, which enhances the overall system throughput at low-complexity. Simulations and analytical results demonstrate the performance of our scheme in impulse noise environment as well as AWGN and fading multi-input multi-ouput (MIMO) channels.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.2
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• pp.101-111
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• 2008

This paper introduces a high-speed Reed-Solomon(RS) decoder, which reduces the hardware complexity, and presents an RS decoder based FEC architecture which is used for 40Gb/s optical communication systems. We introduce new pipelined degree computationless modified Euclidean(pDCME) algorithm architecture, which has high throughput and low hardware complexity. The proposed 16 channel RS FEC architecture has two 8 channel RS FEC architectures, which has 8 syndrome computation block and shared single KES block. It can reduce the hardware complexity about 30% compared to the conventional 16 channel 3-parallel FEC architecture, which is 4 syndrome computation block and shared single KES block. The proposed RS FEC architecture has been designed and implemented with the $0.18-{\mu}m$ CMOS technology in a supply voltage of 1.8 V. The result show that total number of gate is 250K and it has a data processing rate of 5.1Gb/s at a clock frequency of 400MHz. The proposed area-efficient architecture can be readily applied to the next generation FEC devices for high-speed optical communications as well as wireless communications.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.4
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• pp.939-947
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• 2010

The LDPC(Low-Density Parity-Check) code, which is one of the channel encoding methods in IEEE 802.11n wireless LAN standard, has superior error-correcting capabilities. Since the hardware complexity of LDPC decoder is high, it is very important to take into account the trade-offs between hardware complexity and decoding performance. In this paper, the effects of LLR(Log-Likelihood Ratio) approximation on the performance of MSA(Min-Sum Algorithm)-based LDPC decoder are analyzed, and some optimal design conditions are derived. The parity check matrix with block length of 1,944 bits and code rate of 1/2 in IEEE 802.11n WLAN standard is used. In the case of $BER=10^{-3}$, the $E_b/N_o$ difference between LLR bit-widths (6,4) and (7,5) is 0.62 dB, and $E_b/N_o$ difference for iteration cycles 6 and 7 is 0.3 dB. The simulation results show that optimal BER performance can be achieved by LLR bit-width of (7,5) and iteration cycle of 7.

• Proceedings of the KIEE Conference
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• 2006.10c
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• pp.428-430
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• 2006

This paper proposes a new means of performance optimization for multimedia algorithm utilizing the Microscopic DVS (Dynamic Voltage Scaling). The Microscopic DVS technique controls the operating frequency and the supply voltage levels dynamically according to the processing requirement for each frame of multimedia data. The huffman decoding algorithm of MPEG-2 AAC audio decoder is optimized to maximize the power saving efficiency of Microscopic DVS technique. The experimental results show the reduction of computational complexity by more than 30% and the reduction of power consumption by more than 17% compared with those of the conventionally fast method.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.55 no.12
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• pp.544-546
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• 2006

This paper proposes a new means of performance optimization for multimedia algorithm utilizing the Microscopic DVS (Dynamic Voltage Scaling). The Microscopic DVS technique controls the operating frequency and the supply voltage levels dynamically according to the processing requirement for each frame of multimedia data. The huffman decoding algorithm of MPEG-2 AAC audio decoder is optimized to maximize the power saving efficiency of Microscopic DVS technique. The experimental results show the reduction of computational complexity by more than 30% and the reduction of power consumption by more than 17% compared with those of the conventionally fast method.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.4 no.4
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• pp.434-440
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• 2003

Since Jacquine introduced the image coding algorithm using fractal theory, many fractal image compression algorithms providing good quality at low bit rate have been proposed by Fisher and Beaumount et al.. But a problem of the previous implementations is that the decoding rests on an iterative procedure whose complexity is image-dependent. This paper proposes an iterative-free fractal image decoding algorithm to reduce the decoding time. In the proposed method, under the encoder previously with the same codebook image as an initial image to be used at the decoder, the fractal coefficients are obtained through calculating the similarity between the codebook image and an input image to be encoded. As the decoding process can be completed with received fractal coefficients and predefined initial image without repeated iterations, the decoding time could be remarkably reduced.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.3A
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• pp.324-330
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• 2004

In this paper, we propose the TCM(Trellis coded modulation) decoding scheme that reduces the number of operations in branch metric with STBC(space time block codes) channel information and present the implementation results. The proposed TCM decoding scheme needs only 1 signal point in each TCM subset. Using bias point scheme, It detects the minimum distance symbol. The proposed TCM decoding scheme can reduce the branch metric calculations. In case of 16QAM 8 subset, the reduction ratio is about 50％ and for 64QAM 8 subset, about 80％ reduction can be obtained. The results of logic synthesis for the TCM and STBC decoder with the proposed scheme are 57.6K gate count.