• The Transactions of the Korean Institute of Electrical Engineers A
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• v.48 no.10
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• pp.1344-1348
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• 1999

This paper proposes concurrent event propagation technique for timing analysis. The technique makes it possible to find several input vectors and sensitizable paths at the same time. The concurrent event propagation technique is based on the event driven simulation and the timing analysis technique with boolean equations. The technique propagates as many events as possible at the same time while preventing propagation of boolean terms which do not sensitize paths. Since events do not propagate through false paths, the longest path which successfully propagates events to one of the primary outputs is one of the longest sensitizable paths. The technique can speed up timing analysis by unifying path sensitization and maximum delay calculation.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.1
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• pp.1-9
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• 1998

In the circuit model that outputs are latched and input vectors are successively applied at inputs, the gate resizing approach to reduce the delay of the critical pathe may not improve the performance. Since the clock period is etermined by delays of both long and short paths in combinational circuits, the performance (clock period) can be optimized by decreasing the delay of the longest path, or increasing the delay of the shortest path. In order to achieve the desired clock period of a circuit, gates lying in sensitizable long and short paths can be selected for resizing. However, the gate selection in path sensitization approach is a difficult problem due to the fact that resizing a gate in shortest path may change the longest sensitizable path and viceversa. For feasible settings of the clock period, new algorithms and corresponding gate selection methods for resizing are proposed in this paper. Our new gate selection methods prevent the delay of the longest path from increasing while resizing a gate in the shortest path and prevent the delay of the shortest path from decreasing while resizing a gate in the longest sensitizable path. As a result, each resizing step is guaranteed not to increase the clock period. Our algorithmsare teted on ISCAS85 benchmark circuits and experimental results show that the clock period can beoptimized efficiently with out gate selection methods.

• Proceedings of the Korean Operations and Management Science Society Conference
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• 2002.05a
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• pp.8-14
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• 2002

This article presents a new algorithm for the K Shortest Paths Problem which develops initial K shortest paths, and repeal to expose hidden shortest paths with dual approach and to replace the longest path in the present K paths. The initial solution which comprises K shortest paths among shortest paths to traverse each arc is made from bidirectional Dijkstra algorithm. When a crossing node that have two or more inward arcs is found at least three time by turns in this K shortest paths, one inward arc of this crossing node, which has minimum detouring distance, is chosen, and a new path is exposed with joining a detouring subpath from source to this inward arc and a spur of a feasible path from this crossing node to sink. This algorithm, requires worst case time complexity of $O(Kn^2),\;and\;O(n^2)$ in the case $K{\leq}3$.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.13 no.1
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• pp.435-451
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• 2019

Impossible differential cryptanalysis is an essential cryptanalytic technique and its key point is whether there is an impossible differential path. The main factor of influencing impossible differential cryptanalysis is the length of the rounds of the impossible differential trail because the attack will be more close to the real encryption algorithm with the number becoming longer. We provide the upper bound of the longest impossible differential trails of several important block ciphers. We first analyse the national standard of the Russian Federation in 2015, Kuznyechik, which utilizes the 16-byte LFSR to achieve the linear transformation. We conclude that there is no any 3-round impossible differential trail of the Kuznyechik without the consideration of the specific S-boxes. Then we ascertain the longest impossible differential paths of several other important block ciphers by using the matrix method which can be extended to many other block ciphers. As a result, we show that, unless considering the details of the S-boxes, there is no any more than or equal to 5-round, 7-round and 9-round impossible differential paths for KLEIN, Midori64 and MIBS respectively.

• Journal of KIISE:Computer Systems and Theory
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• v.31 no.1_2
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• pp.19-26
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• 2004

In this paper, we investigate the longest fault-free paths joining every pair of vertices in a double loop network with faulty vertices and/or edges, and show that a bipartite double loop network G(mn；1, m) is strongly hamiltonian-laceable when the number of faulty elements is two or less. G(mn；1, m) is bipartite if and only if m is odd and n is even.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.12
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• pp.229-240
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• 1995

This paper proposes a new weighted random pattern testing technique to detect path delay faults in combinational logic circuits. When computing the probability of signal transition at primitive logic elements of CUT(Circuit Under Test) by the primary input, the proposed technique uses the information on the structure of CUT for initialization vectors and vectors generated by pseudo random pattern generator for test vectors. We can sensitize many paths by allocating a weight value on signal lines considering the difference of the levels of logic elements. We show that the proposed technique outperforms existing testing method in terms of test length and fault coverage using ISCAS '85 benchmark circuits. We also show that the proposed testing technique generates more robust test vectors for the longest and near-longest paths.

• Journal of the Korean Operations Research and Management Science Society
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• v.26 no.3
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• pp.79-94
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• 2001

This paper presents a new algorithm for the K shortest paths Problem which develops initial K shortest paths, and repeat to expose hidden shortest paths with dual approach and to replace the longest path in the present K paths. The initial solution comprises K shortest paths among shortest paths to traverse each arc in a Double Shortest Arborescence which is made from bidirectional Dijkstra algorithm. When a crossing node that have two or more inward arcs is found at least three time by turns in this K shortest paths, there may be some hidden paths which are shorter than present k-th path. To expose a hidden shortest path, one inward arc of this crossing node is chose by means of minimum detouring distance calculated with dual variables, and then the hidden shortest path is exposed with joining a detouring subpath from source to this inward arc and a spur of a feasible path from this crossing node to sink. If this exposed path is shorter than the k-th path, the exposed path replaces the k-th path. This algorithm requires worst case time complexity of O(Kn$^2$), and O(n$^2$) in the case k$\leq$3.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.6
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• pp.771-780
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• 2016

Detecting a set of longest paths is one of the crucial steps in static timing analysis and optimization. Recently, the process variation during manufacturing affects performance of the circuit design due to nanometer feature size. Measuring the performance of a circuit prior to its fabrication requires a considerable amount of computation time because it requires multi-corner and multi-mode analysis with process variations. An efficient algorithm of detecting the K-most critical paths in multi-corner multi-mode static timing analysis (MCMM STA) is proposed in this paper. The ISCAS'85 benchmark suite using a 32 nm technology is applied to verify the proposed method. The proposed K-most critical paths detection method reduces about 25% of computation time on average.

• IE interfaces
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• v.15 no.3
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• pp.247-255
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• 2002

For the recent multimedia service, the network should be fast, stable, and reliable. In order to provide reliability of the network, certain survivability of the network, which guarantees it's functions even though there is some failure on the network, should be satisfied. Also, for a pair of nodes on the network, there must be paths of which numbers of hops are within a certain limit for realtime service between them. In this paper, we propose a longest shortcut method for solving the survivable network design problems with hop limit. Through the computational results, we compare the efficiency of the method with an existing shortest shortcut method and find that the proposed method is more efficient than the shortest shortcut method.

• Journal of KIISE:Computer Systems and Theory
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• v.31 no.7
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• pp.397-401
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• 2004

In an edge-weighted(positive, negative, or zero weights are possible) tree, we want to solve the problem of finding a longest path such that the sum of the weights of the edges in the path is non-negative. We present an algorithm to find a longest non-negative path of a degree 3 tree in Ο(n log n) time, where n is the number of nodes in the tree.