• The Transactions of the Korea Information Processing Society
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• v.4 no.1
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• pp.311-323
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• 1997

This paper presents a fast fault simulation system for detecting stuck-at faults in mixed-level combinational logic circuits with gale level and switch -level primitives. For a practical fault simulator, the types are not restricted to static switch-level and/or gate-level circuits, but include dynamic switch-level circuits. To efficiently handle the multiple signal contention problems at wired logic elements, we propose a six-valued logic system and its logic calculus which are used together with signal strength information. As a basic algorithm for the fault simulation process, a well -known gate-level parallel pattern single fault propagation(PPSFP) technique is extended to switch-level circuits in order to handle pass-transistor circuits and precharged logic circuits as well as static CMOS circuits. Finally, we demonstrate the efficiency of our system through the experimental results for switch-level ISCAS85 benchmark combinational circuits and various industrial mixed-level circuits.

• Journal of the Korea Society for Simulation
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• v.15 no.1
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• pp.11-17
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• 2006

This paper shows a case study of designing a PLC logic simulator that was developed to simulate and verify PLC control programs for nuclear plant systems. The nuclear control system requires strict restrictions rather than normal process control system does, as it works with a high-risky and dangerous nuclear plant. One is that it should assure the safeness of the control programs by exploiting severe testing. The other restriction is that the control programs should be executed fast enough such that they could control multi devices concurrently in real-time. To cope with these restrictions, we devised a logic compiler which generates C-code programs from given PLC logic programs. Once the logic program was translated into C-code, the program could be analyzed by conventional software analysis tools and could be used to construct a fast logic simulator after cross-compiling, in fact, that is a kind of compiled-code simulator.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.18 no.2
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• pp.324-334
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• 2017

The simulators for a plant unit master control (UMC) developed by domestic or overseas researchers have been developed for operator-training purposes. UMC simulators normally constructed at the end of the plant construction, despite the UMC logics, should be simulated to pre-check many signal interfaces within the power generation systems. Because of the differences in construction schedule, it is difficult for logic designers or commissioning engineers to simulate the UMC logic during the design or commissioning stage. In this background, this paper proposes a simulation method that can be used easily by plant logic designers or operators in the MATLAB Simulink programming environment. The core of the UMC is realized with a unique simulation algorithm based on mathematical analysis and functional blocks combination. In addition, an integer-based configuration was proposed to realize the plant target value control for the equipment in the logic. With these simulation methods, functions, e.g., load distribution, high-low limitations, frequency compensation, etc. were simulated. The results showed that the plant UMC logic can be simulated in Simulink without a plant simulator. The various functions proposed in this paper can provide useful information about Simulink-based simulation design for plant logic designers or commissioning engineers during the power plant construction period.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 1993.06a
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• pp.785-788
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• 1993

This paper presents the prototype framework for automated integration of CMOS current-mode fuzzy logic circuits using an intelligent module approach. The library of modules representing the standard fuzzy logic operators was built. These modules were finally used to synthesized sophisticated fuzzy logic units. Fuzzy unit designs were made based upon the results of a newel methodology of the current mirror-based fuzzy logic function synthesis. This methodology is actually incorporated into the presented framework. As an example, the membership function unit was synthesized, simulated, and the final layout was generated using the presented framework. Finally, the fuzzy logic controller unit (FLC) was generated using the proposed framework. Simulation as well as measurement results show unquestionable advantages of the proposed fuzzy logic function integration system over the classical design methodology with respect to the area, relative error and performance.

• Korean System Dynamics Review
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• v.12 no.4
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• pp.125-156
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• 2011

The information service management models developed thus far have put their focuses mostly on technical dimensions of information systems (IS), finding their rationale from the goods-dominant logic (GDL) that IS as goods has value in itself. Information systems, however, is nothing more than a mechanism by which value is delivered to the users. According to the service-dominant logic (SDL), value is created and determined not at the time serve is made by the providers but at the time it is consumed by the users. The users therefore should be regarded as active value creators not as passive consumers of the value delivered by the providers. Based on the service-dominant logic, DISQM (Dynamic Information Service Quality Model) is developed. DISQM's backbone is designed in causal loop diagrams referring to and reinterpreting in systems thinking the 'Parasuraman, Zeithaml & Berry's GAP Model' and 'SERVQUAL' as an operational tool for the GAP Model, and the main IS success constructs are mapped onto the model exploiting the 'DeLone & MacLean's IS Success Model'. With VENSIM simulation software, this paper also shows how DISQM works in computer-simulation settings. After confirming DISQM's validity with the base simulation run, two scenarios are developed for the exemplary purpose and tested in terms of IS quality, service quality, and net benefits from the service for the public information service. Implications from the simulation runs are also discussed.

• KSCI Review
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• v.2 no.1
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• pp.121-129
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• 1995

Fault simulation of logic circuits is an important part of the test-generation process. It is used for the propose of generation fault dictionaries or for the verification of the adequacy of tests. In this paper, a backtrace fault simulation is proposed to test generation. This is consists of 3 part ; initialization phase for given circuit, backtrace fault simulation phase to find fault list and reevaluation phase to list event. The main idea of this algorithm is to retain a minimum fault list by cutting uncontrollable lines of path when a logic event occurs in backward tracing phases. And the simulator is revaluates a fault list associated with the output of an element only if logic event occurs at any of its inputs when a list event occurs at one of its primary inputs. It reguires a O(n) memory space complexity. where n is a number of signal lines for the given circuits. Several examples are given to illustrate the power of this algorithm.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.467-468
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• 2008

In this paper, a logic family, the transmission gate CMOS(TG CMOS) is proposed, which combines the transmission gate and pass transistor resulting in a different configuration from traditional full CMOS. In the simulation, basic cells comprising this logic are designed and their dynamic responses are analyzed. The simulation shows their performance is exceeding that of conventional full CMOS.

• Journal of the Korea Society for Simulation
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• v.5 no.2
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• pp.73-84
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• 1996

As circuits are larger and more complicated, logic simulation is playing a very important role in design verification. A good simulator should be fast and accurate, but unknown values in 3 value simulator may generate X-propagation problem which makes inaccurate output values. In this paper, a new partitioning method is devised to deal with X-propagation problem efficiently and an efficient algorithm is developed which is able to optimize time and accuracy by controlling partition depths. The results prove the effectiveness of the new simulation algorithm using some benchmark circuits.

• KIPS Transactions on Computer and Communication Systems
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• v.4 no.3
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• pp.85-90
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• 2015

In this paper, anew parallel event-driven logic simulation is proposed. As the proposed prediction-based parallel event-driven simulation method uses both prediction data and actual data for the input and output values of local simulations executed in parallel, the synchronization overhead and the communication overhead, the major bottleneck of the performance improvement, are greatly reduced. Through the experimentation with multiple designs, we have observed the effectiveness of the proposed approach.

• Proceedings of the KIEE Conference
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• 1996.11a
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• pp.291-293
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• 1996

Logic simulation is playing a very important role for design verification as circuits are larger and more complicated. However unknown values in 3 value simulators may generate the X-propagation problem which makes inaccurate output values. In this paper, a new partitioning method and a new simulation algorithm are developed to deal with the X-propagation problem efficiently. The new algorithm can optimize simulation time and accuracy by controlling partition depth. Benchmark results prove the effectiveness of the new simulation algorithm.