• Title/Summary/Keyword: logic gates

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Fanout Constrained Logic Synthesis (Fanout 제약 조건하의 논리 회로 합성)

  • 이재형;황선영
    • Journal of the Korean Institute of Telematics and Electronics A
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    • v.28A no.5
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    • pp.387-397
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    • 1991
  • This paper presents the design and implementation of a performance-driven logic synthesis system that automatically generates circuits satisfying the given timing and fanout constraints in minimal silicon area. After performing technology independent and dependent optimization, the system identifies and resynthesizes the gates with large loading delay due to excessive fanouts to eliminate the critical path. Experimental results for MCNC benchmark circuits show that proposed system generates the circuits with less delay by up to 20%.

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Computer-Aided Design of Sequential Logic Circuits (Case of Asynchronous Sequential Logic Circuits) (컴퓨터를 이용한 순차 논리 회로의 설계(비동기 순차논리 회로의 경우)

  • 김병철;조동섭;황희영
    • The Transactions of the Korean Institute of Electrical Engineers
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    • v.33 no.2
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    • pp.47-55
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    • 1984
  • This paper is concerned with a computer-aided state assignment, that is, coding race-free internal states of asynchronous sequential circuits, and a method for minimizing the combinational network of asynchronous sequential circuits. The FORTRAN version of the peoposed algorithm results in race-free state assignments and reduction of the number of connections and gates with near minimal hardware cost. Some examples are designed by the proposed computer program to illustrate the algorithm in this paper. Finally, results are compared with those of the other methods.

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An Implementation of PC based digital logic interface (디지털로직 인터페이스 개발)

  • 조현섭;송용화;김희숙
    • Proceedings of the KAIS Fall Conference
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    • 2003.06a
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    • pp.208-210
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    • 2003
  • In spite of the presence of various kind of Integrated Circuits it's not always easy to get the right part. Besides, it is hard to find a vendor fer a small quantity consumers like who develop prototype applications. In this study, we've tried to get the logical signals from the PC based device we've developed that correspondents with the real ICs. It can emulate decoder ICs, multiplexers, demultiplexers and basic logic gates.

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Two Phase Clocked Adiabatic Static CMOS Logic and its Logic Family

  • Anuar, Nazrul;Takahashi, Yasuhiro;Sekine, Toshikazu
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.10 no.1
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    • pp.1-10
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    • 2010
  • This paper proposes a two-phase clocked adiabatic static CMOS logic (2PASCL) circuit that utilizes the principles of adiabatic switching and energy recovery. The low-power 2PASCL circuit uses two complementary split-level sinusoidal power supply clocks whose height is equal to $V_{dd}$. It can be directly derived from static CMOS circuits. By removing the diode from the charging path, higher output amplitude is achieved and the power consumption of the diode is eliminated. 2PASCL has switching activity that is lower than dynamic logic. We also design and simulate NOT, NAND, NOR, and XOR logic gates on the basis of the 2PASCL topology. From the simulation results, we find that 2PASCL 4-inverter chain logic can save up to 79% of dissipated energy as compared to that with a static CMOS logic at transition frequencies of 1 to 100 MHz. The results indicate that 2PASCL technology can be advantageously applied to low power digital devices operated at low frequencies, such as radio-frequency identifications (RFIDs), smart cards, and sensors.

Design of A Logic/Timing Extraction System for Higher-level Design Verification (상위단계 설계 검증을 위한 논리/타이밍 추출 시스템의 설계)

  • 이용재;문인호;황선영
    • Journal of the Korean Institute of Telematics and Electronics A
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    • v.30A no.2
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    • pp.76-85
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    • 1993
  • This paper describes the design of a technology-independent logic, function, and timing extraction system from SPICE-like network descriptions. Technology-independent extraction mechanism is provided in the form of technology files containing the rules for constructing logic gates and functional blocks. The designed system can be more effectively used in cell-based design by describing the cells to be extracted. Timing extraction is performed by using a linear RC gate delay model which takes interconnection delay into account. Experimental results show that estimated delay is within 10 percents for logic gate circuits when compared with SPICE. Through higher-level design descriptions obtained by extraction, design cycles can be considerably reduces.

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Tabular Methods for the Design of Multivalued Logic Circuits Using CCD (CCD를 이용한 다치논린회로의 설계에 관한 Tabular법)

  • 송홍복;정만영
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.13 no.5
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    • pp.411-421
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    • 1988
  • This paper offers a method to design CCD four-valued circuits using the tabular method. First, the four-valued logic function is decomposed by hand-calculation or computer program. Nest, the algorithm is derived form the tabular method based on the decomposition process to realize the DDC four-valued circuit. According to this algorithm, the two-variable four valued logic function is decomposed and realized by CCD network with four basic gates. The synthesis method in this paper proves that the number of devices and cost is considerably reduces as compared with the existing methods to realize the same logic functions.

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A SDL Hardware Compiler for VLSI Logic Design Automation (VLSI의 논리설계 자동화를 위한 SDL 하드웨어 컴파일러)

  • Cho, Joung Hwee;Chong, Jong Wha
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.23 no.3
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    • pp.327-339
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    • 1986
  • In this paper, a hardware compiler for symbolic description language(SDL) is proposed for logic design automation. Lexical analysis is performed for SDL which describes the behavioral characteristics of a digital system at the register transfer level by the proposed algorithm I. The algorithm I is proposed to get the expressions for the control unit and for the data transfer unit. In order to obtain the network description language(NDL) expressions equivalent to gate-level logic circuits, another algorithm, the the algorithm II, is proposed. Syntax analysis for the data formed by the algorithm I is also Performed using circuit elements such as D Flip-Flop, 2-input AND, OR, and NOT gates. This SDL hardware compiler is implemented in the programming language C(VAX-11/750(UNIX)), and its efficiency is shown by experiments with logic design examples.

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Design of a Technology Mapping System for Logic Circuits (논리 회로의 기술 매핑 시스템 설계)

  • 김태선;황선영
    • Journal of the Korean Institute of Telematics and Electronics A
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    • v.29A no.2
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    • pp.88-99
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    • 1992
  • This paper presents an efficient method of mapping Boolean equations to a set of library gates. The proposed system performs technology mapping by graph covering. To select optimal area cover, a new cost function and local area optimization are proposed. Experimental results show that the proposed algorithm produces effective mapping using given library.

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