• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.11
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• pp.1-10
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• 1998

The advent of deep submicron technologies in the age of portable electronic systems creates a moving target for CAB algorithms, which now need to reduce power as well as delay and area in the existing design methodology. This paper presents a resynthesis algorithm for logic decomposition on mapped circuits. The existing algorithm uses a Huffman encoding, but does not consider glitches and effects on logic depth. The proposed algorithm is to generalize the Huffman encoding algorithm to minimize the switching activity of non-critical subcircuits and to preserve a given logic depth. We show how to obtain a transition-optimum binary tree decomposition for AND tree with zero gate delay. The algorithm is tested using SIS (logic synthesizer) and Level-Map (LUT-based FPGA lower power technology mapper) and shows 58%, 8% reductions on power consumptions, respectively.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.59 no.2
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• pp.359-362
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• 2010

In this study, inverter logic circuits on a plastic substrate are built with two top-gate FETs in series on a single ZnO nanowire. The voltage transfer characteristics of the ZnO nanowire-based inverter logic circuit exhibit a clear inverting operation. The logic swing, gain and transition width of the inverter logic circuit is about 90 %, 1.03 and 1.2 V, respectively. The result of mechanical bending cycles of the inverter logic circuit on a plastic substrate shows that the stable performance is maintained even after many hundreds of bending cycles.

• Journal of the Korean Institute of Telematics and Electronics
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• v.24 no.2
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• pp.338-346
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• 1987

This paper describes a method for verifying whether a given geometrical layout correcdtly reflects the original logic level description. The logic description extracted from layout data was directly compadred with the original logic diagram generated at logic level design stage where the logic diagram is represented as a weighted multi-place graph. The comparison is based on graph isomorphism and error messages(error categories and locations)are invoked if any difference is found between the two logic descriptions. An efficient partitioning algorithm which consists of two steps, candidate selection and equal weight partitioning procedure, enables the entire verification process to occur in O(n log n) time.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.12
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• pp.198-208
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• 1995

BiCMOS circuit consist of CMOS part which constructs logic function, and bipolar part which drives output load. Test to detect stuck-open faults in BiCMOS circuit is important, since these faults do sequential behavior and are represented as transition faults. In this paper, proposes a method for efficiently detecting transistor stuck-open faults in BiCMOS circuit by transforming them into slow-to=rise transition and slow-to-fall transition. In proposed method, BiCMOS circuit is transformed into equivalent gate-level circuit by dividing it into pull-up part which make output 1, and pull-down part which make output 0. Stuck-open faults in transistor are modelled as transition fault in input line of gate level circuit which is transformed from given circuit. Faults are detceted by using pull-up part gate level circuit when expected value is '01', or using pull-down part gate level circuit when expected value is '10'. By this method, transistor stuck-open faults in BiCMOS circuit are easily detected using conventional gate level test generation algorithm for transition fault.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2014.11a
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• pp.10-11
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• 2014

In a 2-dimensional (2D) Discrete Cosine Transform (DCT) hardware, a significant fraction of the total hardware area is contributed by the combinational logic used to perform 1-dimensional (2D) transform. The size of the non-combinational logic i.e. the transpose memory is dictated by the size of the largest transform supported. Hence, the optimization of hardware area is performed mainly for 1D-transform combinational logic. This paper demonstrates the use of Multiple Constant Multiplication (MCM) algorithm to reduce the combinational logic area. Partial optimizations are also described for the cases where the direct use of MCM algorithm doesn't meet the timing constraint. Experimental results show that 46% improvement in gate count is achieved for 32 point 1D DCT transform logic after using MCM optimization.

• Journal of the Korean Institute of Telematics and Electronics
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• v.24 no.4
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• pp.701-707
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• 1987

This paper is concerned with an accurate delay time modling of the ED MOS logic gates and its application to the multiple delay logic simulator. The proposed delay model of the ED MOS logic gate takes account of the effects of not only the loading conditions but also the slope of the input waveform. Defining delay as the time spent by the current imbalance of the active inverter to charge and discharge the output load, with respect to physical reference levels, rise and fall model delay times are obtained in an explicit formulation, using optimally weighted imbalance currents at the end points of the voltage transition. A logic simulator which uses multiple rise/fall delays based on the model as decribed in the above has been developed. The new delay model and timing verification method are evaluated with repect to delay accuracy and execution time.

• Journal of the Optical Society of Korea
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• v.16 no.4
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• pp.432-442
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• 2012

In this paper, we propose, analyze and simulate the performances of some new plasmonic logic gates in two dimensional plasmonic waveguides with nanodisk resonators, using the numerical method of finite difference time domain (FDTD). These gates, including XOR, XNOR, NAND, and NOT, can provide the highly integrated optical logic circuits. Also, by cascading and combining these basic logic gates, any logic operation can be realized. These devices can be utilized significantly in optical processing and telecommunication devices.

• The Transactions of the Korea Information Processing Society
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• v.4 no.1
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• pp.311-323
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• 1997

This paper presents a fast fault simulation system for detecting stuck-at faults in mixed-level combinational logic circuits with gale level and switch -level primitives. For a practical fault simulator, the types are not restricted to static switch-level and/or gate-level circuits, but include dynamic switch-level circuits. To efficiently handle the multiple signal contention problems at wired logic elements, we propose a six-valued logic system and its logic calculus which are used together with signal strength information. As a basic algorithm for the fault simulation process, a well -known gate-level parallel pattern single fault propagation(PPSFP) technique is extended to switch-level circuits in order to handle pass-transistor circuits and precharged logic circuits as well as static CMOS circuits. Finally, we demonstrate the efficiency of our system through the experimental results for switch-level ISCAS85 benchmark combinational circuits and various industrial mixed-level circuits.

• Progress in Superconductivity
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• v.4 no.2
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• pp.127-131
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• 2003

We have designed and measured an SFQ(Single Flux Quantum) OR gate for a superconducting ALU (Arithmetic Logic Unit). To optimize the circuit, we used WRspice, XIC and Lmeter for simulations and layouts. The OR gate was consisted of a Confluence Buffer and a D Flip-Flop. When a pulse enters into the OR gate, the pulse does not propagate to the other input port because of the Confluence Buffer. A role of D Flip-Flip is expelling the data when the clock is entered into D Flip-Flop. For the measurement of the OR gate operation, we attached three DC/SFQs, three SFQ/DCs and one RS Flip -Flop to the OR gate. DC/SFQ circuits were used to generate the data pulses and clock pulses. Input frequency of 10kHz and 1MHzwere used to generate the SFQ pulses from DC/SFQ circuits. Output data from OR gate moved to RS flip -Flop to display the output on the oscilloscope. We obtained bias margins of the D Flip -Flop and the Confluence Buffer from the measurements. The measured bias margins $\pm$38.6% and $\pm$23.2% for D Flip-Flop and Confluence Buffer, respectively The circuit was measured at the liquid helium temperature.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.28A no.12
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• pp.65-72
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• 1991

A cost model of test generation is presented in this paper. The cost of flat gate-level and hierarchical modular level test generation for combinational logic circuits are modeled. The model shows that the cost of hierarchical test generation grows as GlogGunder some assuptions, while the cost of gate-level test generation grows $G^2<$/TEX>, where G is the number of gates in a circuit under test. The cost model derived in this paper is used to explain why some test generation techniques are faster and why hierarchical test generators should be faster than flat test generators on large circuits.