• Journal of Advanced Navigation Technology
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• v.16 no.1
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• pp.62-69
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• 2012

Multiple-control Toffoli(MCT) gates are macro-level multiple-valued gates needing quantum technology dependent primitive gates, and have been used in Galois Field sum-of-product (GFSOP) based synthesis of quantum logic circuit. Reversible logic is very important in quantum computing for low-power circuit design. This paper presents a reversible GF4 multiplier at first, and GF4 multiplier based quaternary MCT gate realization is also proposed. In the comparisons of MCT gate realization, we show the proposed MCT gate can reduce considerably primitive gates and delays in contrast to the composite one of the smaller MCT gates in proportion to the multiple-control input increase.

• The Journal of the Korea institute of electronic communication sciences
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• v.14 no.1
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• pp.87-96
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• 2019

Flexible organic light-emitting diode (OLED) displays with organic thin-film transistors (OTFTs) backplanes have been studied. A gate driver is required to drive the OLED display. The gate driver is integrated into the panel to reduce the manufacturing cost of the display panel and to simplify the module structure using fabrication methods based on low-temperature, low-cost, and large-area printing processes. In this paper, pseudo complementary metal oxide semiconductor (CMOS) logic gates are implemented using OTFTs for the gate driver integrated in the flexible OLED display. The pseudo CMOS inverter and NAND gates are designed and fabricated on a flexible plastic substrate using inkjet-printed OTFTs and the same process as the display. Moreover, the operation of the logic gates is confirmed by measurement. The measurement results show that the pseudo CMOS inverter can operate at input signal frequencies up to 1 kHz, indicating the possibility of the gate driver being integrated in the flexible OLED display.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.58 no.8
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• pp.1580-1584
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• 2009

We have theoretically analyzed the monolithic integration of vertical cavity lasers with depleted optical thyristor (VCL-DOT) structure and experimentally demonstrated optical logic gates such as AND-gate, OR-gate, and INVERTER implemented by VCL-DOT for an optical programmable gate array. The optical AND and OR gates have been realized by changing a input bias of the single VCL-DOTs and all kinds of optical logic functions are also implemented by adjusting an intensity of the reference input beams into the differential VCL-DOTs. To achieve the high sensitivity, high slope efficiency and low threshold current, a small active region of lasing part and a wide detecting area are simultaneously designed by using a selective oxidation process. The fabricated devices clearly show nonlinear s-shaped current-voltage characteristics and lasing characteristics of a low threshold current with 0.65 mA and output spectrum at 854 nm.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1999.05a
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• pp.21-25
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• 1999

In order to remove minority carries of the base region at changing signal in conventional bipolar logic circuit, we made transistor which is composed of NPN transistor shortened buried layer under the Base region, PNP transistor which is merged in base, epi layer and substrate. Also the Ring-Oscillator for measuring transmission time-delay per gate was designed as well. In the result, we get amplitude of logic voltage of 200mV, the minimum of transmission delay-time of 211nS, and the minimum of transmission delay-time per gate of 7.26ns in AC characteristic output of Ring-Oscillator connected Gate.

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.48 no.10
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• pp.1317-1326
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• 1999

As the integration ratio and operation speed increase, it has become an important problem to estimate the dissipated power during the design procedure as a method to reduce the TTM(time to market). This paper proposed a prediction model to estimate the maximum dissipated power of a CMOS logic gate. This model uses a calculational method. It was formed by including the characteristics of MOSFETs of which a CMOS gate consists, the operational characteristics of the gate, and the characteristics of the input signals. As the modeling process, a maximum power estimation model for CMOS inverter was formed first, and then a conversion model to convert a multiple input CMOS gate into a corresponding CMOS inverter was proposed. Finally, the power model for inverter was applied to the converted result so that the model could be applied to a general CMOS gate. For experiment, several CMOS gates were designed in layout level by $0.6{\mu}m$ layout design rule. The result by comparing the calculated results with those from HSPICE simulations for the gates showed that the gate conversion model has within 5% of the relative error rate to the SPICE and the maximum power estimation model has within 10% of the relative error rate. Thus, the proposed models have sufficient accuracies. Also in calculation time, the proposed models was more than 30 times faster than SPICE simulation. Consequently, it can be said that the proposed model could be used efficiently to estimate the maximum dissipated power of a CMOS logic gate during the design procedure.

• JSTS:Journal of Semiconductor Technology and Science
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• v.6 no.1
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• pp.52-58
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• 2006

Single-electron transistor (SET)-based logic cells and SET/FET hybrid integrated circuits have been fabricated on SOI chips. The input-output voltage transfer characteristic of the SET-based complementary logic cell shows an inverting behavior where the output voltage gain is estimated to be about 1.2 at 4.2K. The SET/FET output driver, consisting of one SET and three FETs, yields a high voltage gain of 13 and power amplification with a wide-range output window for driving next circuit. Finally, the SET/FET literal gate for a multi-valued logic cell, comprising of an SET, an FET and a constant-current load, displays a periodic voltage output of high/low level multiple switching with a swing as high as 200mV. The multiple switching functionality of all the fabricated logic circuits could be enhanced by utilizing a side gate incorporated to each SET component to enable the phase control of Coulomb oscillations, which is one of the unique characteristics of the SET-based logic circuits.

• The Journal of the Korea Contents Association
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• v.18 no.1
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• pp.10-18
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• 2018

This paper presents a method to resynthesize logic of a programmed FPGA from a bitstream file that is a downloaded file for Xilinx FPGA (Field Programmable Gate Array). It focuses on reconfiguring the LUT (Look Up Table) logic. The bitstream data is compared and analyzed considering various situations and various input variables such as composing other logics using the same netlist or synthesizing the same logic at various positions to find a structure of the bitstream. Based on the analyzed bitstream, we construct a truth table of the LUT by implementing various logic for one LUT. The proposed algorithm extracts the logic of the LUT based on the truth table of the generated LUT and the bitstream. The algorithm determines the input and output pins used to implement the logic in the LUT. As a result, we extract a gate level logic from a bitstream file for the targeted Xillinx FPGA.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.10
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• pp.93-101
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• 1995

The evaluation of the logic capability and the library generation method of the multiplexor-based logic module is described. Optimizing logic module for silicon area and logic capability is essential to build a efficient FPGAs(Field-Programmable Gate Arrays). Because the multiplexor-based logic module can implement a large number of functions, it presents difficulties for library-based approaches. However, the logic functions of the logic module can be significantly reduced by lmiting the number of variables and sum-of-products and by removing same functions with different variable ordering using algorithm presented in this paper.

• Nuclear Engineering and Technology
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• v.44 no.6
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• pp.697-708
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• 2012

The majority of instrumentation and control (I&C) systems in today's nuclear power plants (NPPs) are based on analog technology. Thus, most existing I&C systems now face obsolescence problems. Existing NPPs have difficulty in repairing and replacing devices and boards during maintenance because manufacturers no longer produce the analog devices and boards used in the implemented I&C systems. Therefore, existing NPPs are replacing the obsolete analog I&C systems with advanced digital systems. New NPPs are also adopting digital I&C systems because the economic efficiencies and usability of the systems are higher than the analog I&C systems. Digital I&C systems are based on two technologies: a microprocessor based system in which software programs manage the required functions and a programmable logic device (PLD) based system in which programmable logic devices, such as field programmable gate arrays, manage the required functions. PLD based systems provide higher levels of performance compared with microprocessor based systems because PLD systems can process the data in parallel while microprocessor based systems process the data sequentially. In this research, a bistable trip logic in a reactor protection system (RPS) was developed using very high speed integrated circuits hardware description language (VHDL), which is a hardware description language used in electronic design to describe the behavior of the digital system. Functional verifications were also performed in order to verify that the bistable trip logic was designed correctly and satisfied the required specifications. For the functional verification, a random testing technique was adopted to generate test inputs for the bistable trip logic.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.1
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• pp.91-105
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• 2016

Carbon Nanotube Field-Effect Transistors (CNTFETs) have been studied as candidates for post Si CMOS owing to the better electrostatic control and high mobility. To enhance the immunity against short - channel effects (SCEs), the novel channel and gate engineered architectures have been proposed to improve CNTFETs performance. This work presents a comprehensive study of the influence of channel and gate engineering on the CNTFET switching, high frequency and circuit level performance of carbon nanotube field-effect transistors (CNTFETs). At device level, the effects of channel and gate engineering on the switching and high frequency characteristics for CNTFET have been theoretically investigated by using a quantum kinetic model. This model is based on two-dimensional non-equilibrium Green's functions (NEGF) solved self - consistently with Poisson's equations. It is revealed that hetero - material - gate and lightly doped drain and source CNTFET (HMG - LDDS - CNTFET) structure can significantly reduce leakage current, enhance control ability of the gate on channel, improve the switching speed, and is more suitable for use in low power, high frequency circuits. At circuit level, using the HSPICE with look - up table(LUT) based Verilog - A models, the impact of the channel and gate engineering on basic digital circuits (inverter, static random access memory cell) have been investigated systematically. The performance parameters of circuits have been calculated and the optimum metal gate workfunction combinations of ${\Phi}_{M1}/{\Phi}_{M2}$ have been concluded in terms of power consumption, average delay, stability, energy consumption and power - delay product (PDP). In addition, we discuss and compare the CNTFET-based circuit designs of various logic gates, including ternary and binary logic. Simulation results indicate that LDDS - HMG - CNTFET circuits with ternary logic gate design have significantly better performance in comparison with other structures.