• ETRI Journal
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• v.39 no.1
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• pp.124-134
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• 2017

Data races are one of the most difficult types of bugs in concurrent multithreaded systems. It requires significant time and cost to accurately detect bugs in complex large-scale programs. Although many race detection techniques have been proposed by various researchers, none of them are effective in all aspects. In this paper, we compare the performance of five recent dynamic race detection techniques: FastTrack, Acculock, Multilock-HB, SimpleLock+, and causally precedes (CP) detection. We experimentally demonstrate the strengths and weaknesses of these dynamic race detection techniques in terms of their detection capability, running time, and runtime overhead using 20 benchmark programs with different characteristics. The comparison results show that the detection capability of CP detection does not differ from that of FastTrack, and that SimpleLock+ generates the lowest overhead among the hybrid detection techniques (Acculock, SimpleLock+, and Multilock-HB) for all benchmark programs. SimpleLock+ is 1.2 times slower than FastTrack on average, but misses one true data race reported from Mutilock-HB on the large-scale benchmark programs.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.3
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• pp.582-586
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• 2005

This paper presents a new structure of Phase Locked Loop(PLL) which changes its loop bandwidth according to the locking status. The proposed PLL consists of a conventional PLL and, Locking Status Indicator(LSI). The LSI decides the operating bandwidth of loop filler. When the PLL becomes out of lock, the PLL increases the loop bandwidth and achieves fast locking. When the PLL becomes in-lock, this PLL decreases the loop bandwidth and minimizes phase noise output. The PLL can achieve fast locking and low phase noise output at the same time. Proposed PLL's locking time is less than $40{\mu}s$ and spur is 76.1dBc. It is simulated by HSPICE in a Hynix CMOS $0.35{\mu}m$ Process.

• Journal of Ocean Engineering and Technology
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• v.26 no.5
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• pp.25-30
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• 2012

This study examined the use of LIT (lock-in infrared thermography) to detect defects in the welded parts of ships and offshore structures. A quantitative analysis was used with the filtering and texture measurement of image processing techniques to find the optimized experimental condition. We verified the reliability of our methods by applying image processing techniques in order to normalize the evaluations of comparative images that showed a phase difference. In addition, it was found that a low to mid-range intensity of light exposure on the surface showed good results, whereas high exposure did not provide significant results. A lock-in frequency of around 0.1 Hz was satisfactory regardless of the intensity of the light source. In addition, making the integration time of the thermography camera inversely proportional to the intensity of the exposed light source during the experiment provided good results.

• The Journal of Information Technology
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• v.12 no.4
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• pp.11-17
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• 2009

In this paper, frequency synthesizer for radar system is designed and developed. Optimizing the phase noise and lock time, each module is designed as two-type PLL circuit, and then the performance of PLL frequency synthesizer is compared. The experiment result shows the lock time of 70 usec, the phase noise of less then 100 dBc, the bandwidth above 500MHz.

• Journal of the military operations research society of Korea
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• v.25 no.1
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• pp.199-214
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• 1999

The Constructive Battle Simulation Model is very important to the recent military training for the substitution of the field training. However, real battlefield systems operate under real-time conditions, they are inherently distributed, concurrent and dynamic. In order to reflect these properties by the computer-based simulation systems which represent real world processes, we have been developing constructive simulation model for several years. Conventionally, scheduling and resource allocation activities which have timing constraints, we elaborated on these issues and developed the simulation system on commercially available hardware and operating system with lock-free resource allocation scheme and rate monotonic scheduling.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.51 no.1
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• pp.23-33
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• 2002

A hysteresis control is widely used to control output current of inverter. A hysteresis bandwidth is affected by system parameters such as source voltage, device on/off time, load inductance and resistance. The frequency limiter is used to protect switching devices overload. In the conventional hysteresis controller, a lock-out circuit with D-latch and timer is used to device protection circuit. But switching delay time and harmonic components are appeared in output current. In this paper the performance of lock-out circuit is tested, and new circuit for switching device fault protection is proposed ad it's performance is simulated.

• Proceedings of the KIEE Conference
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• 2003.07a
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• pp.418-420
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• 2003

The fault current limiting characteristics at the initial fault time for flux-lock type high-Tc superconducting fault current limiter(SFCL) were investigated. The amplitude of initial fault current of the flux-lock type SFCL was dependent on the inductance ratio of coil 1 and 2. After fault current limiting mode was analyzed, we compared the calculated value with the experimental one for the initial fault current. The effect of initial fault current due to the inductance ratio of coil 1 and 2 on fault current limiting characteristics was discussed.

• Korean Journal of Optics and Photonics
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• v.11 no.5
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• pp.330-334
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• 2000

A new pha~e lock loop (PLL) IS proposed and demonstrated fat clock recovery from 40 Gblt/s time-dIvision-multiplexed (TDM) optical pulse tri.lin, The proposed clock lecovery scheme lmproves the Jitter effecl cOlmng from the clock. pulse laser of harmonically-mode locked flber laser The cross-corrdation frequency component between the optical Signa] and an optical clock pulse tram is deteCled as a fonr-wave-mixing (FWM) SIgnal generated in SOA. The lock-in freqnency range of the clod. recovery IS found to be within 10 KHz. 0 KHz.

• The Journal of the Acoustical Society of Korea
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• v.15 no.2E
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• pp.60-68
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• 1996

In this paper, we implement the door lock system based on pattern matching technique for speaker recognition using DTW. In this study, major features of our system are summarized as follows:(1) Make the average reference pattern using DTW. This method keeps the high recognition rate compared with the other systems whose performances degrade rapidly as time goes on. (2) Use F-ratio values of the cepstral coefficients. We find that the weighted cepstral reveals an effect on intensifying the difference between th customer and the imposter. The system hardware is composed of two parts : the door lock part and the speaker recognition processing part. We use an 8051 microprocessor in the door lock park for serial communication with host processor to open or close the lock. Using our system, we obtain speaker recognition rate of about 99.5%.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.20 no.9
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• pp.812-815
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• 2007

To apply the superconducting fault current limiter(SFCL) into a power system, the analysis for its recovery characteristics as well as the consideration for its cooperation with other protecting machine such as a circuit breaker is required. The recovery characteristics of the flux-lock type SFCL like its current limiting characteristics are dependent on the winding direction of two coils. In this paper, the experiments of the current limiting and the recovery characteristics of the flux-lock type SFCL with YBCO thin film were performed. From the analysis on the experimental results due to the winding direction of two coils, the limited fault current in case of the additive polarity winding was observed to be lower than that for the case of the subtractive polarity winding. In addition, the recovery time was found to be faster in case of the additive polarity winding compared to the subtractive polarity winding.