• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.24 no.2
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• pp.136-140
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• 2011

The fault current limiting characteristics of the flux-lock type superconducting fault current limiter (SFCL) using a transformer winding were investigated. The suggested flux-lock type SFCL consists of two parallel connected coils on an iron core and the transformer winding connected in series with one of two coils. In this SFCL, the high-TC superconducting (HTSC) element was connected with the secondary side of the transformer. The short-circuit experimental devices to analyze the fault current limiting characteristics of the flux-lock type SFCL using the transformer winding were constructed. Through the short-circuit tests, the flux-lock type SFCL using transformer winding was shown to perform more effective fault current limiting operation compared to the previous flux-lock type SFCL without the transformer winding from the viewpoint of the quench occurrence and the recovery time of the HTSC element.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.07a
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• pp.601-604
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• 2003

The magnetic field generated in the iron core, which is required for the magnetic field to link each coil of the flux-lock type reactor, affects the fault current limiting characteristics of the flux-lock type high-Tc superconducting fault current limiter(SFCL). By applying numerical analysis for equivalent circuit of flux-lock type SFCL, the magnetic field induced in the iron core including currents of each coil was investigated. Through the analysis of magnetic field, we have analyzed that the magnetic field linked the 3rd coil, which is wound in the iron core, prevents the saturation of the iron core, but decreases the impedance of the flux-lock type SFCL.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.20 no.11
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• pp.995-999
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• 2007

We investigated the characteristics of a flux-lock type superconducting fault current limiter(SFCL) considering magnetization characteristic of iron core. The flux-lock type SFCL, like other types of SFCLs using the iron core, undergoes the saturation of the iron core during the initial fault time. Therefore, if the design to prevent the saturation of the iron core is considered, the effective fault current limiting operation can be achieved. Through the analysis for its equivalent circuit including the magnetization characteristic of the iron core, the limiting impedance of the flux-lock type SFCL was drawn. The magnetization currents and the limited currents of SFCL, which were dependent on the winding direction and the turns' ratio between two coils, were investigated from the short circuit experiment. It was confirmed that their experimental results agreed with the analysis ones.

• Journal of the Computational Structural Engineering Institute of Korea
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• v.29 no.1
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• pp.9-18
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• 2016

The slender structures such as high rise building or marine riser are highly susceptible to dynamic force exerted by fluid-structure interactions among which vortex-induced vibration(VIV) is the main cause of dynamic unstability of the structural system. If VIV occurs in natural frequency regime of the structure, fatigue failure likely happens by so-called lock-in phenomenon. This study presents the numerical analysis of dynamic behavior of both structure and fluid in the lock-in regimes and investigates the subjacent phenomena to hold the resonance frequency in spite of the change of flow condition. Unsteady and laminar flow was considered for a two-dimensional circular cylinder which was assumed to move freely in 1 degree of freedom in the direction orthogonal to the uniform inflow. Fluid-structure interaction was implemented by solving both unsteady flow and dynamic motion of the structure sequentially in each time step where the fluid domain was remeshed considering the movement of the body. The results show reasonable agreements with previous studies and reveal characteristic features of the lock-in phenomena. Not only the lift force but also drag force are drastically increasing during the lock-in regime, the vertical displacement of the cylinder reaches up to 20% of the diameter of the cylinder. The correlation analysis between lift and vertical displacement clearly show the dramatic change of the phase difference from in-phase to out-of-phase when the cylinder experiences lock-in. From the results, it can be postulated that the change of phase difference and flow condition is responsible for the resonating behavior of the structure during lock-in.

• Transactions of the Korean Society of Automotive Engineers
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• v.7 no.7
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• pp.229-241
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• 1999

The paper describes the development of the ABS(Anti-Lock Bracke Sytem) real-time simulator which is composed of the real hydraulic modulator, the brake system, and the control software. This useful too supports the development enviornment of the ABS in great flexible mamer. It offers an efficient and cost-effective method of ABS development which includes the various realistic road conditons, the vehicle characteristics , and the brake characteristics. The performance of the ABS is compared with the normal braking results. Thepresented experimental results are braking on the high friction road, thetransient friction road(high to low , low to high), the split friction road, and the high friction road with steer angle. The paper shows the effectiveness and the safety of the ABS compared with the normal brake system , and the powerful and conventient tool in developing the ABS.

• Journal of information and communication convergence engineering
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• v.10 no.2
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• pp.187-193
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• 2012

A 1 GHz CMOS fast-lock phase-locked loop (PLL) is proposed to support the quick wake-up time of mobile consumer electronic devices. The proposed fast-lock PLL consists of a conventional charge-pump PLL, a frequency-to-digital converter (FDC) to measure the frequency of the input reference clock, and a digital-to-analog converter (DAC) to generate the initial control voltage of a voltage-controlled oscillator (VCO). The initial control voltage of the VCO is driven toward a reference voltage that is determined by the frequency of the input reference clock in the initial mode. For the speedy measurement of the frequency of the reference clock, an FDC with a parallel architecture is proposed, and its architecture is similar to that of a flash analog-to-digital converter. In addition, the frequency-to-voltage converter used in the FDC is designed simply by utilizing current integrators. The circuits for the proposed fast-lock scheme are disabled in the normal operation mode except in the initial mode to reduce the power consumption. The proposed PLL was fabricated by using a 0.18-${\mu}m$ 1-poly 6-metal complementary metal-oxide semiconductor (CMOS) process with a 1.8 V supply. This PLL multiplies the frequency of the reference clock by 10 and generates the four-phase clock. The simulation results show a reduction of up to 40% in the worstcase PLL lock time over the device operating conditions. The root-mean-square (rms) jitter of the proposed PLL was measured as 2.94 ps at 1 GHz. The area and power consumption of the implemented PLL are $400{\times}450{\mu}m^2$ and 6 mW, respectively.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.10
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• pp.76-81
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• 2013

A new phase frequency detector based digital phase-locked loop (PLL) of 125 MHz was designed using the 130 nm CMOS technology library consisting of inverting edge detectors along with a typical digital phase-locked loop to reduce the lock time and jitter for mid-frequency applications. XOR based inverting edge detectors were used to obtain a transition earlier than the reference signal to change the output more quickly. The HSPICE simulator was used in a Cadence environment for simulation. The performance of the digital phase-locked loops with the proposed phase frequency detector was compared with that of conventional phase frequency detector. The PLL with the proposed detector took $0.304{\mu}s$ to lock with a maximum jitter of approximately 0.1142 ns, whereas the conventional PLL took a minimum of $2.144{\mu}s$ to lock with a maximum jitter of approximately 0.1245 ns.

• Journal of IKEEE
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• v.23 no.3
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• pp.800-804
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• 2019

This paper presents a dual-loop sub-sampling digital PLL for a 2.4 GHz IoT applications. The PLL initially performs a divider-based coarse lock and switches to a divider-less fine sub-sampling lock. It achieves a low in-band phase noise performance by enabling the use of a high resolution time-to-digital converter (TDC) and a digital-to-time converter (DTC) in a selected timing range. To remove the difference between the phase offsets of the coarse and fine loops, a phase offset calibration scheme is proposed. The phase offset of the fine loop is estimated during the coarse lock and reflected in the coarse lock process, resulting in a smooth transition to the fine lock with a stable fast settling. The proposed digital PLL is designed by SystemVerilog modeling and Verilog-HDL and fully verified with simulations.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.05a
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• pp.900-902
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• 2015

Doors are to be the most basics of our lives from opening, closing and even keeping our property. Hence, doors have been innovated to blend in and make our daily lives more convenient. However, we find it difficult to open and close the doors manually of offices or tour zones, where they open and close at a precise time everyday. To solve this, we added a dimension of time to previous Door Locks. By this, every door with this specific door lock will open and close at a certain time we want them to open or close. Also, through the application you can control the time or use it to open and close the doors remotely. In order to do this, we systemed the door lock time system based on Java Programing language to make it easy to communicate and open or close the doors through smart phone applications, with the C programming language for the ATmega128 which will open and close the doors.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.5
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• pp.1027-1034
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• 2017

Recently, OTP (One-time-Password) log-in methods have been used in many areas to prevent leakage of personal information and enhance security. The OTP method is primarily used for security of bank personal account, this is one of the sophisticated security ways in which one time password is generated and checked to enhance security. Digital door locks frequently used in everyday life require convenience and safety simultaneously. Meanwhile, related technologies for digital door locks are evolving, but methods for enhancement of security are still unsatisfactory. Generally, the digital door lock using password input type has been most commonly used and especially it provides more convenience, but it has some problems such as password exposure and password oblivion. Therefore, in this study, we propose and implement the OTP-based digital door lock system with enhanced security and convenience features but without the risk of password exposure and oblivion.