• 제목/요약/키워드: lock-time

검색결과 371건 처리시간 0.036초

모바일 계산환경에서 거래 관리를 위한 동시성 제어 (Concurrency Control for Transaction Management in Mobile Computing)

  • Rhee, Hae-kyung
    • 전자공학회논문지CI
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    • 제40권6호
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    • pp.22-31
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    • 2003
  • 데이터베이스 시스템에서 기존의 동시성 제어전략은 통신 중단이 빈번히 발생하는 모바익 컴퓨팅 환경 하에서는 부적절하다. 모바일 컴퓨팅에서는 거래들을 처리하기 위한 시간이 극히 제한적이다. 이러한 시간을 가장 효율적으로 활용하기 위해서는 단기거래위주의 처리가 바람직하다 통신 중단으로 인한 Service Handoff는 특히 단기거래인 경우 모바일 거래들의 성능을 저하시킬 수 있다. 이타적 잠금 기법은 lock/unlock연산 이외에 donate 연산을 사용하기 때문에 단기거래 들에 대해 효율적이다. 모바일 컴퓨팅에서 이타적 잠금 기법을 사용했을 경우 단기거래의 성능은 향상될 수 있다.

LTCC 기법을 이용한 ITS용 초소형 RF 송신기 모듈의 구현 (An Implementation of Miniature RF Transmitter Module for ITS Applications by Using LTCC Technique)

  • 윤기호
    • 한국전자파학회논문지
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    • 제16권10호
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    • pp.1020-1027
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    • 2005
  • 본 논문에서는 지능형 교통망(ITS)에 사용될 수 있도록 5.8 GHz 대역에서 경제적이며 초소형 RF 송신기 모듈을 구현하였다. LTCC 방식으로 설계하여 회로의 소형화와 함께 전기적 성능을 개선하였다. 제작된 모듈은 ASK 데이터 변조 장치, 주파수 합성기, 송신용 전력 증폭 회로 등으로 구성되었으며 모듈 크기는 0.8 CC이다. 측정결과 1.024 Mbps 데이터를 5.8 GHz의 주파수 대역으로 직접 ASK 변조시켜 출력 10 dBm 이상과 인접 채널 간섭비 -40 dBc 등의 RF 송신 성능을 나타낸다. 송신기의 신호원으로서 설계 제작된 주파수 합성기는 26 usec의 채널 이동시간(lock time)을 보여주며 중심 주파수에서 1 MHz 떨어진 지점에서 -115 dBc/Hz의 우수한 위상 잡음 특성을 나타낸다.

PLC 코드 작성을 위한 공정 분석 및 적용 방법 (The Process Analysis and Application Methods for PLC Code Programming)

  • 구락조;여성주;이강구;홍상현;박창목;박상철;왕지남
    • 산업공학
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    • 제21권3호
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    • pp.294-301
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    • 2008
  • Agile and flexible manufacturing systems make it mandatory that a control program should have features such as agility, flexibility, and reusability in order to run manufacturing unit smoothly. PLCs are the most frequently used control program in manufacturing systems. PLC programs are mostly programmed by subcontraction, which makes correction of code very difficult. As a result, it may cause delay during down time and ramp up time which leads to big loss of revenue and goodwill. To prevent delay during the times, this paper proposes systematic process analysis and application method for programmable logic controller like LLD (Ladder Logic Diagram). The proposed method uses modified human-error investing techniques for documentation and transforming technique to program LLD from the documentation. Furthermore, this paper demonstrates an example of piston mechanism to explain the proposed method.

설계 개선을 통한 선박의 계류 시스템 최적화 사례 소개 (Introduction of Optimized Design of Anchoring System through Design Modification of Pocket and Chain Compressor)

  • 이재훈
    • 대한조선학회 특별논문집
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    • 대한조선학회 2011년도 특별논문집
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    • pp.55-62
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    • 2011
  • Although the performance of the commercial vessel has been dramatically improved through innovations, there has been no big changes on the traditional anchoring method of commercial vessels, both on design and operation until now. In this paper, two cases of design modifications were introduced for optimized design of pocket type anchor handling, which resulted in improved performance of the vessel's anchoring. From the first time fully balanced type anchors were applied on vessels in Korean shipyard, main design problem on this application was that the anchor doesn't normally slide into the pocket when the anchor fluke is not in line with pocket, as the anchor freely rotates by the swivel on forerunner. In order to prevent the problem, swivel has been deleted on the forerunner to prevent anchor rotation until now, but this solution caused problems such as twist lock of anchor chain, restriction of windlass direction, etc. On this paper, one of the solution is introduced to overcome the design problem by tilting the hawse pipe to some extent, which makes anchor turned at the time anchor ring touches the pocket skirt and that it properly slides into the pocket. Secondly, one of the solution is introduced to overcome misalignment problem between anchor chain cable and roller of chain compressor, which has been frequently occurred, by modification of roller design.

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마찰에너지율을 이용한 타이어 제동거리 예측 (Braking Distance Estimation using Frictional Energy Rate)

  • 전도형;최주형;조진래;김기전;우종식
    • 대한기계학회:학술대회논문집
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    • 대한기계학회 2004년도 춘계학술대회
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    • pp.519-524
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    • 2004
  • This study is concerned with the braking distance estimation using frictional energy rate. First, steady state rolling analysis is performed, and using this result, the braking distance is estimated. Dynamic rolling analysis during entire braking time period is impratical, so that this study divides the vehicle velocity by 10km/h to reduce the analysis time. The multiplication of the slip rate and the shear stress provides the frictional energy rate. Using frictional energy rate, total braking distance is estimated, In addition, ABS(Anti-lock Brake System) is considered, and two type of slip ratios are compared, One is 15% slip ratio for the ABS condition, and the other is 100% slip ratio which leads lo the almost same braking distance as the elementary kinematic theory. A slip ratio is controlled by angular velocity in ABAQUS/Explicit, A 15% slip ratio gives the real vehicle's braking distance when the frictional energy occurred al disk pad is included. Disk pad's frictional energy rate is calculated by the theoretical approach.

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개선된 자동 주파수 보정회로를 이용한 광대역 클록 발생기 설계 (A Wideband Clock Generator Design using Improved Automatic Frequency Calibration Circuit)

  • 정상훈;유남희;조성익
    • 전기학회논문지
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    • 제60권2호
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    • pp.451-454
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    • 2011
  • In this paper, a wideband clock generator using novel Automatic frequency calibration(AFC) scheme is proposed. Wideband clock generator using AFC has the advantage of small VCO gain and wide frequency band. The conventional AFC compares whether the feedback frequency is faster or slower then the reference frequency. However, the proposed AFC can detect frequency difference between reference frequency with feedback frequency. So it can be reduced an operation time than conventional methods AFC. Conventional AFC goes to the initial code if the frequency step changed. This AFC, on the other hand, can a prior state code so it can approach a fast operation. In simulation results, the proposed clock generator is designed for DisplayPort using the CMOS ring-VCO. The VCO tuning range is 350MHz, and a VCO frequency is 270MHz. The lock time of clock generator is less then 3us at input reference frequency, 67.5MHz. The phase noise is -109dBC/Hz at 1MHz offset from the center frequency. and power consumption is 10.1mW at 1.8V supply and layout area is $0.384mm^2$.

MAXIMUM BRAKING FORCE CONTROL UTILIZING THE ESTIMATED BRAKING FORCE

  • Hong, D.;Hwang, I.;SunWoo, M.;Huh, K.
    • International Journal of Automotive Technology
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    • 제8권2호
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    • pp.211-217
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    • 2007
  • The wheel slip control systems are able to control the braking force more accurately and can be adapted to different vehicles more easily than conventional ABS (Anti-lock Brake System) systems. In realizing the wheel slip control systems, real-time information such as the tire braking force at each wheel is required. In addition, the optimal target slip values need to be determined depending on the braking objectives such as minimum braking distance and stability enhancement. In this paper, a robust wheel slip controller is developed based on the adaptive sliding mode control method and an optimal target slip assignment algorithm is proposed for maximizing the braking force. An adaptive law is formulated to estimate the braking force in real-time. The wheel slip controller is designed based on the Lyapunov stability theory considering the error bounds in estimating the braking force and the brake disk-pad friction coefficient. The target slip assignment algorithm searches for the optimal target slip value based on the estimated braking force. The performance of the proposed wheel slip control system is verified in HILS (Hardware-In-the-Loop Simulator) experiments and demonstrates the effectiveness of the wheel slip control in various road conditions.

멀티플레이 실시간 전략 시뮬레이션 게임을 위한 동기화 알고리즘들의 성능 평가 (Performance Evaluation of Synchronization Algorithms for Multi-play Real-Time Strategy Simulation Games)

  • 강민석;김경식;오삼권
    • 한국정보처리학회:학술대회논문집
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    • 한국정보처리학회 2008년도 추계학술발표대회
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    • pp.1280-1283
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    • 2008
  • MOG(Multiplayer Online Game)의 네트워크 성능은 네트워크 부하량과 사용자의 입력에 대한 반응속도로 측정 가능하다. 본 논문은 MOG의 일종인 실시간 전략 시뮬레이션 분야에서 게임 동기화에 이용되는 프레임 잠금(frame lock) 알고리즘과 게임 턴(game turn) 알고리즘을 소개하고 그 성능을 평가한 결과를 제시한다. 또한 동기화 알고리즘들을 쉽게 교체하여 효율적인 평가를 진행할 수 있는 MOG 서버 구조도 제시한다.

Development of a CAN-based Real-time Simulator for Car Body Control

  • Kang, Ki-Ho;Seong, Sang-Man
    • 제어로봇시스템학회:학술대회논문집
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    • 제어로봇시스템학회 2005년도 ICCAS
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    • pp.444-448
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    • 2005
  • This paper presents a developing procedure of the CAN-based real-time simulator for car body control, aiming at replacing the actual W/H (Wiring Harness) and J/B(Junction Box) couple eventually. The CAN protocol, as one kind of field-bus communication, defines the lowest 2 layers of the ISO/OSI standard, namely, the physical layer(PL) and the data link layer(DLL), for which the CSMA/NBA protocol is generally adopted. For CPU, two PIC18Fxx8x's are used because of their built-in integration of CAN controller, large internal FLASH memory (48K or 64K), and their costs. To control J/B's and actuators, 2 controller boards are separately implemented, between which CAN lines communicate through CAN transceivers MCP255. A power motor for washing windshield, 1 door lock motor, and 6 blink lamps are chosen for actuators of the simulator for the first stage. For the software architecture, a polling method is used for the fast global response time despite its slow individual response time. To improve the individual response time and to escape from some eventual trapped-function loops, High/Low ports of the CPU are simply used, which increases the stability of the actuator modules. The experimental test shows generally satisfactory results in normal transmitting / receiving function and message trace function. This simulator based on CAN shows a promising usefulness of lighter, more reliable and intelligent distributed body control approach than the conventional W/H and J/B couple. Another advantage of this approach lies in the distributed control itself, which gives better performance in hard real-time computing than centralized one, and in the ability of integrating different modules through CAN.

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Fractional-N PLL (Phase-Locked Loop) 주파수 합성기 설계 (Fractional-N PLL Frequency Synthesizer Design)

  • 김선철;원희석;김영식
    • 대한전자공학회논문지TC
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    • 제42권7호
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    • pp.35-40
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    • 2005
  • 본 논문에서는 900MHz 대역 중저속 무선 통신용 칩에 이용되는 3차 ${\Delta}{\sum}$ modulator를 사용한 Fractional-N PLL 주파수 합성기를 설계 및 제작하였다 우수한 위상노이즈 특성을 얻기 위해 노이즈 특성이 좋은LC VCO를 사용하였다. 그리고 고착시간을 줄이기 위해서 Charge Pump의 펌핑 전류를 주파수 천이 값에 따라 조절할 수 있도록 제작하였고 PFD의 참조 주파수를 3MHz까지 높였다. 또한 참조 주파수를 높이는 동시에 PLL의 최소 주파수 천이 간격을 10KHz까지 줄일 수 있도록 하기위하여 36/37 Fractional-N 분주기를 제작하였다. Fractional Spur를 줄이기 위해서 3차 ${\Delta}{\sum}$ modulator를 사용하였다. 그리고 VCO, Divider by 8 Prescaler, PFD, 및 Charge Pump는 0.25um CMOS공정으로 제작되었으며, 루프 필터는 외부 컴포넌트를 이용한 3차RC 필터로 제작되었다. 그리고 Fractional-N 분주기와 3차 ${\Delta}{\sum}$ modulator는 VHDL 코드로 작성되었으며 Xilinx Spartan2E을 사용한 FPGA 보드로 구현되었다. 측정결과 PLL의 출력 전력은 약 -11dBm이고, 위상노이즈는 100kHz offset 주파수에서 -77.75dBc/Hz이다. 최소 주파수 간격은 10kHz이고, 최대 주파수 천이는 10MHz이고, 최대 주파수 변이 조건에서 고착시간은 약 800us이다.