• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.12 no.5
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• pp.1-9
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• 2012

In this paper, we presents the modeling and implementation of the DDS(Direct Digital synthesizer) driven offset PLL(Pghase Locked Loop) with DAC(Digital Analog Converter) for coarse tune. The PLL synthesizer was designed for minimizing the size and offset frequency and DDS technique was used for ultra low noise and fast lock up time, also DAC was used for coarse tune. The output phase noise was analyzed by superposition theory with the phase noise transfer function and noise source modeling. the phase noise prediction was evaluated by comparing with the measured data. The designed synthesizer has ultra fast lock time within 6 usec and ultra low phase noise performance of -120 dBc/Hz at 10KHz offset frequency.

• Journal of KIISE:Computer Systems and Theory
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• v.27 no.4
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• pp.394-400
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• 2000

The main goal of synchronization is to guarantee exclusive access to shared data and critical sections, and then it makes parallel programs work correctly and reliably. Exclusive access restricts parallelism of parallel programs, therefor efficient synchronization is essential to achieve high performance in shared-memory parallel programs. Many techniques are devised for efficient synchronization, which utilize features of systems and applications. This paper shows the simulation results that existing synchronization methods have inefficiency under CC-NUMA(Cache Coherent Non-Uniform Memory Access) system, and then compares the performance of Freeze&Melt synchronization that can remove the inefficiency. The simulation results present that Test-and-Test&Set synchronization has inefficiency caused by broadcast operation and the pre-defined order of Queue-On-Lock-Bit (QOLB) synchronization to execute a critical section causes inefficiency. Freeze&Melt synchronization, which removes these inefficiencies, has performance gain by decreasing the waiting time to execute a critical section and the execution time of a critical section, and by reducing the traffic between clusters.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.8
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• pp.598-609
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• 2003

This paper describes a CMOS IF PLL frequency synthesizer. The designed frequency synthesizer can be programmed to operate at various intermediate frequencies using different external LC-tanks. The VCO with automatic amplitude control provides constant output power independent of the Q-factor of the external LC-tank. The designed frequency divider includes an 8/9 or 16/17 dual-modulus prescaler and can be programmed to operate at different frequencies by external serial data for various applications. The designed circuit is fabricated using a 0.35${\mu}{\textrm}{m}$ n-well CMOS process. Measurement results show that the phase noise is 114dBc/Hz@100kHz and the lock time is less than 300$mutextrm{s}$. It consumes 16mW from 3V supply. The die area is 730${\mu}{\textrm}{m}$$\times$950${\mu}{\textrm}{m}$.

• Journal of Oral Medicine and Pain
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• v.37 no.4
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• pp.221-225
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• 2012

Disc dislocation without reduction, as known as closed lock, is a clinical condition in which the disc is dislocated from the condyle and does not return to normal position during condylar movement When the condition of disc dislocation without reduction is acute, the initial therapy should include an attempt to reduce or recapture the disc by manual manipulation. When patients report a history of being locked for 1 week or less, manual manipulation is usually successful. In patients with a longer history, success rate tends to decrease rapidly. If the disc has been successfully recaptured, placing an anterior positioning appliance is recommended to prevent clenching on the posterior teeth, which would likely redislocated the disc. But it is hard to make an appliance immediately in the clinic because it takes too much time. And making an appliance using self-curing acrylic resin is not very popular because of its discomfort by odor and working time. Also, if the patient has resin allergy or is under orthodontic treatment, or if it is impossible to control behavior of the patient, it has been restricted to make an appliance immediately. Therefore, to supplement this disadvantages, we tried to confirm about successful short term use of temporary anterior positioning splint made by using putty impression material after manual manipulation in this study.

• The Journal of Korean Society for Radiation Therapy
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• v.23 no.1
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• pp.1-6
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• 2011

Purpose: Immobilizations used in order to maintain the reproducibility of a patient set-up and the stable posture for a long period are important more than anything else for the accurate treatment when the stereotactic body radiotherapy is underway. So the purpose of this study is to adapt the optimum immobilizations for the stereotactic body radiotherapy by comparing two commercial immobilizations with the self-manufactured immobilizations. Materials and Methods: Five people were selected for the experiment and three different immobilizations (A: Wing-board, B: BodyFix system, C: Arm up holder with vac-lock) were used to each target. After deciding on the target's most stable respiratory cycles, the targets were asked to wear a goggle monitor and maintain their respiration regularly for thirty minutes to obtain the respiratory signals. To analyze the respiratory signal, the standard deviation and the variation value of the peak value and the valley value of the respiratory signal were separated by time zone with the self-developed program at the hospital and each tie-downs were compared for the estimation by calculating a comparative index using the above. Results: The stability of each immobilizations were measured in consideration of deviation changes studied in each respiratory time lapse. Comparative indexes of each immobilizations of each experimenter are shown to be A: 11.20, B: 4.87, C: 1.63 / A: 3.94, B: 0.67, C: 0.13 / A: 2.41, B: 0.29, C: 0.04 / A: 0.16, B: 0.19, C: 0.007 / A: 35.70, B: 2.37, C: 1.86. And when all five experimenters wore the immobilizations C, the test proved the most stable value while four people wearing A and one man wearing D expressed relatively the most unstable respiratory outcomes. Conclusion: The self-developed immobilizations, so called the arm up holder vac-lock for the stereotactic body radiotherapy is expected to improve the effect of the treatment by decreasing the intra-fraction organ motions because it keeps the respiration more stable than other two immobilizations. Particularly in case of the stereotactic body therapy which requires the maintenance of set-up state for a long time, the self-developed immobilizations is thought to more useful for stereotactic body radiotherapy rather than the rest two immobilizations with instable respiratory cycle as time passes.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.45 no.4
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• pp.9-21
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• 2008

In this paper, we propose a GNSS-based RF receiver, A high precision localization architecture, and a high sensitivity localization architecture in order to solve the satellite navigation system's problem mentioned above. The GNSS-based RF receiver model should have the structure to simultaneously receive both the conventional GPS and navigation information data of future-usable Galileo. As a result, it is constructed as the multi-band which can receive at the same time Ll band (1575.42MHz) of GPS and El band (1575.42MHz), E5A band (1207.1MHz), and E4B band (1176.45MHz) of Galileo This high precision localization architecture proposes a delay lock loop with the structure of Early_early code, Early_late code, Prompt code, Late_early code, and Late_late code other than Early code, Prompt code, and Late code which a previous delay lock loop structure has. As we suggest the delay lock loop structure of 1/4chips spacing, we successfully deal with the synchronization problem with the C/A code derived from inaccuracy of the signal received from the satellite navigation system. The synchronization problem with the C/A code causes an acquisition delay time problem of the vehicle navigation system and leads to performance reduction of the receiver. In addition, as this high sensitivity localization architecture is designed as an asymmetry structure using 20 correlators, maximizes reception amplification factor, and minimizes noise, it improves a reception rate. Satellite navigation system repeatedly transmits the same C/A code 20 times. Consequently, we propose a structure which can use all of the same C/A code. Since this has an adaptive structure and can limit(offer) the number of the correlator according to the nearby environment, it can reduce unnecessary delay time of the system. With the use of this structure, we can lower the acquisition delay time and guarantee the continuity of tracking.

• Aerospace Engineering and Technology
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• v.3 no.1
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• pp.109-116
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• 2004

In a satellite time management system, the GPS-based clock synchronization technique[1] has the merits of precision time management by knowing the time difference or the error between the OBT(On Board Time) of the internal processors and GPS time every second. It can be realized employing the DPLL(Digital Phase Loop Lock) and FEP(Front End Processor) circuitry for the clock synchronization[2]. In this paper, a refined DPLL & FEP scheme is proposed to provide the precision, stability and robustness of the operation, which is to compensate the errors and noise of the GPS signal, and also to cope with the case when the GPS signal is lost due to several reasons. The simulation and HIL (Hardware In the Loop) test results using the FM(Flight Model) in the course of KOMPSAT-2(Korea Multi Purpose Satellite-2) design and development are illustrated to demonstrate the salient features of this methodology.

• Journal of Mechanical Science and Technology
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• v.20 no.3
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• pp.329-334
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• 2006

This paper presents the evaluation of LPG (Liquefied petroleum gas) regulators for home use. For the evaluation, several properties of the regulators were experimentally analyzed, such as the operation of safety device, the adjusting and lock-up pressure, the adjusting spring and the diaphragm, with respect to the used time of the regulators. Experimental results showed that the initial operation performances of regulators were degraded with increase of the service time and also showed that the degradation of the performance and material property could become serious after about six-year-use of the regulators.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.509-510
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• 2006

FLL (Frequency Locked Loop) is the core block for high-speed transceiver. It incorporates a PLL for fine locking action, and a coarse controller for coarse locking action. A coarse controller compares frequencies coarsely and is applied to detected frequency difference directly. Compare to conventional FLL, frequency is applied to proposed FLL. Proposed FLL in this paper achieves only 5 cycles for coarse lock and total frequency locking time is 5 times faster than conventional FLL. Thus, proposed FLL is more useful to Ethernet transceiver application that requires high-speed data transfer than conventional FLL. Proposed FLL is based on $0.18{\mu}m$ process.

• Proceedings of the KIEE Conference
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• 2000.07d
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• pp.3097-3099
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• 2000

In this paper, we design PLL for a low jitter and fast locking time that is used a new simple precharged CMOS phase frequency detector(PFD). The proposed PFD has a simple structure with using only 18 transistors. Futhermore, the PFD has a dead zone 25ps in the phase characteristic which is important in low jitter applications. The phase and frequency error detection range is not limited as the case of other precharge type PFDs. the simulation results base on a third order PLL are presented to verify the lock in process with the proposed PFD. the PLL using the new PED is designed using 0.25${\mu}m$ CMOS technology with 2.5V supply voltage.