• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.12 no.1
• /
• pp.99-106
• /
• 2001

In this paper, an 1-Watt amplifier for IMT-2000 was designed and fabricated using feedfarward method which has the highest linearity and wide bandwidth. Since feedforward is sensitive to surroundings for example heat, input power level, time and so on, adaptive controller using micro controller is adopted. We fabricated a HPA with 35 dB gain, 40 dBm of 1-dB compression point, and utilized variable attenuator and variable phase shifter using reflection type to cancel loop signal. From the measured results, the fo11owing facts were obtained, in signal loop, main carrier over 35 dB was suppressed and error signal over 30 dB is cancelled in error loop, IMD characteristics above 60 dBc were obtained.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.18 no.4
• /
• pp.602-610
• /
• 1993

The DDA of new active element and the DDA differential integrator are designed. The DDA can be improved matching problems of external elements in op-amp application circuits. The design of DDA is used the transconductance element, differential pair and $2{\mu}m$ design rule. In order to evaluate the performance of the CMOS DDA, we simulated the DDA voltage inverter and the DDA level shifter using the designed CMOS DDA. Furthermore, the grounded resistor and the differential integrator is designed using the CMOS DDA and we found that its characteristics are agreed to OP-AMP differential integrator's. We performed the layout of the CMOS DDA and DDA differential integrator with MOSIS $2{\mu}m$ CMOS technology.

• ETRI Journal
• /
• v.43 no.5
• /
• pp.891-899
• /
• 2021

We propose a stray inductance extraction method on power modules of the few-kilovolts/several-hundred-amperes class using only low voltages and low currents. The method incorporates a double-pulse generator, a level shifter, a switching device, and a load inductor. The conventional approach generally requires a high voltage of more than half the power module's rated voltage and a high current of around half the rated current. In contrast, the proposed method requires a low voltage and low current environment regardless of the power module's rated voltage because the module is measured in a turn-off state. Both theoretical and experimental results are provided. A physical circuit board was fabricated, and the method was applied to three commercial power modules with EconoDUAL3 cases. The obtained stray inductance values differed from the manufacturer-provided values by less than 1.65 nH, thus demonstrating the method's accuracy. The greatest advantage of the proposed approach is that high voltages or high currents are not required.

• Journal of Sensor Science and Technology
• /
• v.31 no.2
• /
• pp.115-119
• /
• 2022

A readout circuit for a mercury-cadmium-telluride (MCT)-amplified mid-wave infrared (IR) photodetector was realized and applied to noncontact chemical agent detectors based on a quantum cascade laser (QCL). The QCL emitted 250 times for each wavelength in 0.2-㎛ steps from 8 to 12 ㎛ with a frequency of 100 kHz and duty ratio of 10%. Because of the nonconstant QCL emission power during on-duty, averaging the photodetector signals is essential. Averaging can be performed in digital back-end processing through a high-speed analog-to-digital converter (ADC) or in analog front-end processing through an integrator circuit. In addition, it should be considered that the 250 IR data points should be completely transferred to a PC during each wavelength tuning period of the QCL. To average and minimize the IR data, we designed a readout circuit using the analog front-end processing method. The proposed readout circuit consisted of a switched-capacitor integrator, voltage level shifter, relatively low-speed analog-to-digital converter, and micro-control unit. We confirmed that the MCT photodetector signal according to the QCL source can be accurately read and transferred to the PC without omissions.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.41 no.11
• /
• pp.1566-1573
• /
• 2016

This paper presents a beam-forming receiver with polyphase In-phase/Quadrature-phase (I/Q) network for airborne communication. In beam-forming receiver, the insertion loss (IL) difference between input path increases the receiver noise figure (NF). The major element for generating IL difference is the impedance variation of phase shifter. In order to maintain a constant IL in every phase, this paper propose a lossless polyphase I/Q network based beam-forming receiver. The proposed lossless polyphase I/Q network has low Q-factor and high impedance for drive back-end VGA (Variable gain amplifier) block with low insertion loss. The 2-stage VGA controls in-phase and quadrature-phase amplitude level for vector summation. The proposed beam-forming receiver prototype is fabricated in TSMC $0.18{\mu}m$ CMOS process. The prototype cover the $360^{\circ}$ with $5.6^{\circ}$ LSB. The average RMS phase error and amplitude error is approximately $1.6^{\circ}$ and 0.3dB.

• Journal of the Institute of Electronics Engineers of Korea SC
• /
• v.43 no.4 s.310
• /
• pp.53-59
• /
• 2006

This paper describes the new design technique of full wave rectifier (FWR) for precise measurement instrument and the chip implementation of this FWR circuit with measurement results. Conventional circuits have some problems of complex design and limited output range( $VDD/2{\sim}VLIIV1IT+$). Proposed FWR circuit was simply designed with two 2x1 MUXs, one high speed comparator, and one differential difference amplifier(DDA). One rail-to-rail differential difference amplifier(DDA) performs the DC level shifting to VSS and 2X amplification simultaneously, and enables the full range ($Vss{\sim}VDD$) operation. The proposed FWR circuits shows more than 50% reduction of chip area and power consumption compared to conventional one. Proposed circuit was implemented with 0.35um 1-poly 2-metal CMOS process. Core size is $150um{\times}450um$ and power dissipation is 840uW with 3.3V single supply.

• Journal of Internet of Things and Convergence
• /
• v.6 no.1
• /
• pp.97-102
• /
• 2020

Multi-Channel Switch ICs for IoT have integrated several solid state structure low ON-resistance bi-directional relay MOS switches with level shifter to drive high voltage and they should be independently controlled by external serialized logic control. These devices are designed for using in applications requiring high-voltage switching control by low-voltage control signals, such as medical ultra-sound imaging, ink-jet printer control, bare board open/short and leakage test system using Kelvin 4-terminal measurement method. This paper describes implementation of analog switch control block and its verification using Field programmable Gate Array (FPGA) test pattern generation. Each block has been implemented using Verilog hardware description language then simulated by Modelsim and prototyped in a FPGA board. Compare to conventional IC, The proposed architecture can be applied to fields where multiple entities need to be controlled simultaneously in the IoT environment and the proposed pattern generation method can be applied to test similar types of ICs.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.44 no.3 s.357
• /
• pp.26-34
• /
• 2007

This Paper describes a chip design technique for body composition analyzer based on the BIA (Bioelectrical Impedance Analysis) method. All the functions of signal forcing circuits to the body, signal detecting circuits from the body, Micom, SRAM and EEPROMS are integrated in one chip. Especially, multi-frequency detecting method can be applied with selective band pass filter (BPF), which is designed in weak inversion region for low power consumption. In addition new full wave rectifier (FWR) is also proposed with differential difference amplifier (DDA) for high performance (small die area low power consumption, rail-to-rail output swing). The prototype chip is implemented with 0.35um CMOS technology and shows the power dissipation of 6 mW at the supply voltage of 3.3V. The die area of prototype chip is $5mm\times5mm$.

• Proceedings of the IEEK Conference
• /
• 2003.07b
• /
• pp.1093-1096
• /
• 2003

본 논문에서는, CMOS APS Image Sensor 내에 포함되어 회로의 면적을 줄인 새롭게 제안된 CMOS Bandgap Reference Bias Generator (BGR)를 온도 및 방사능에 대한 응답을 실험하였다. 제안된 BGR 회로의 설계 목표는 V/sub DD/는 2.5V이상이고, V/sub ref/는 0.75V ± 0.5mV 마진을 가지게 하는 것이다. 제안된 BGR회로는 Level Shifter를 갖는 Differential OP-amp단과 Feedback-Loop를 가지는 Cascode Current Mirror를 사용하여 저전압에서도 동작을 가능하게 하였으며, 높은 출력저항 특성을 가지도록 하였다. 제안된 BGR회로는 하이닉스 0.18㎛ ( triple well two-poly five-metal ) CMOS 공정을 이용하여 Test Chip을 제작하였다. 온도의 변화와 Co-60 노출조건 하에서 Total ionization dose (TID) effect된 BGR회로의 V/sub ref/를 측정하여, 이를 평가하였다. 온도에 대한 반응은, 25℃ 일 때의 V/sub ref/에 대해, 각각 45 ℃에서 0.128%. 70℃에서 0.768% 변화하였다. 그리고 온도가 25℃일 때 50krad와 100krad의 방사능을 조사 하였을 경우, V/sub ref/는 각각 2.466%, 그리고 4.612% 변화하였다.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.45 no.10
• /
• pp.53-58
• /
• 2008

This paper proposes a new set of instructions to improve the packet processing capacity of a network processor. The proposed set of instructions is able to achieve more efficient packet processing by accelerating integration of packet headers. Furthermore, a hardware configuration dedicated to processing overlay instructions was designed to reduce additional hardware cost. For this purpose, the basic architecture for the network processor was designed using LISA and the overlay block was optimized based on the barrel shifter. The block was synthesized to compare the area and the operation delay, and allocated to a C-level macro function using the compiler known function (CKF). The improvement in performance was confirmed by comparing the execution cycle and the execution time of an application program. Experiments were conducted using the processor designer and the compiler designer from Coware. The result of synthesis with the TSMC ($0.25{\mu}m$) from Synopsys indicated a reduction in operation delay by 20.7% and an improvement in performance of 30.8% with the proposed set of instructions for the entire execution cycle.