• Transactions of the Korean Society of Mechanical Engineers
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• v.18 no.8
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• pp.2139-2157
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• 1994

In order to understand the delamination between leadframe and epoxy molding compound in an electronic packaging of surface mounting type, the stress intensity factor, T-stress and J-integral in fracture mechanics are obtained. The effects of geometry, material properties and molding process temperature on the delamination are investigated taking into account the temperature dependence of the material properties, which simulates as more realistic condition. As the crack length increases the J-integral increases, which suggest that the crack propagates if it starts growing from the small size. The effects of the material properties and molding process temperature on stress intensity factor, T-stress is and J-integral are less significant than the chip size for the practical cases considered here. The T-stress is negative in all eases, which is in agreement with observation that interfacial crack is not kinked until the crack approaches the edge of the leadframe.

• International Journal of Precision Engineering and Manufacturing
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• v.5 no.1
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• pp.36-41
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• 2004

The blanking of thin sheet metal using progressive dies is an important process on production of precision electronic machine parts such as IC leadframe. This paper summarizes the results of simulating the progressive blanking process by means of LS/DYNA. In order to verify the influence of blanking order on the final lead profile and deformed configuration, simulation technique has been proposed and analyzed using a commercial FEM code, LS/DYNA. The results of FE-simulations are in good agreement with the experimental result. After then, to construct rule base in progressive blanking process, FE-simulation has been performed using a simple model. Based on this result rule base is set up and then the blanking order of inner lead is rearranged. Consequently, from the results of FE-simulation using suggested method in this paper, it is possible to predict the shift of lead to manufacture high precision lead frame in progressive blanking process. The proposed method can give more systematic and economically feasible means for designing progressive blanking process.

• Journal of the Korean institute of surface engineering
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• v.36 no.3
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• pp.242-250
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• 2003

Electrodeposition of Ni was carried out on copper substrate from Ni Sulfamate bath by DC and high frequency pulse current. During the electroplating, bath temperature was steady $60^{\circ}C$ , agitation was applied. Morphology and surface roughness of electrodeposits was investigated with the AFM. Crystalline structure of electrodeposits was investigated with XRD. Also, surface electric resistivity was investigated with 4-point probe. The result of crystalline structure by X-ray diffractometer, in the case of DC, <200> direction was dominant growing direction. But in the case of PC, the ratio of <200> direction vs. other direction decreased. As the pulse frequency increased, the enhanced properties of deposits were shown. With increasing frequency, the degree of surface properties increased DC more than that of PC, eg surface morphology, roughness and the degree of compactness of grains. With increasing duty cycle, the surface properties such as the degree of the morphology, roughness and electroconductivity was deteriorated.

• Journal of the Microelectronics and Packaging Society
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• v.7 no.4
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• pp.17-22
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• 2000

In this paper, methods to analyze wire sweep during the semiconductor chip encapsulation have been studied. The wire sweep analysis is used to analyze the deformation of bonding wires that connect the chip to the leadframe during encapsulation. The analysis is done using either analytical solutions or numerical simulation. The analytical solution is used for rough but fast calculation of wire sweep. The results from the numerical simulation are closest to the experimental results.

• JSTS:Journal of Semiconductor Technology and Science
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• v.3 no.3
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• pp.107-113
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• 2003

Microelectronics device performance and its reliability are directly related to and controlled by its constituent materials and their microstructure. Specific processes used to form and shape the materials microstructure need to be controlled in order to achieve the ultimate device performance. Examples of front-end and back-end ULSI processes, packaging process, and novel optical storage materials are given to illustrate such process-structure-property-reliability relationship. As more novel materials are introduced to meet the new requirements for device shrinkage, such under-standing is indispensable for future generation process development and reliability assessment.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2012.05a
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• pp.135-135
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• 2012

세계 환경유해물질 규제에 대응하여 반도체 substrate의 Pb-free solution의 일환으로 등장한 PPF (Pre-Plated Frame)는 패키지공정 조립성은 물론, 자동차 반도체와 같은 고 신뢰성 및 low cost 요구를 만족하기 위해 초박막 고품질의 도금층과 Sub-micro scale의 rough treatment 와 같은 미세 표면제어 기술, 그리고 Au wire로부터 Cu wire 로의 전환에 대응하는 최적화된 도금층 구조로 발전하고 있다. 이러한 기술적인 진화를 거듭해온 이 기술은 다양한 반도체 substrate에 광범위하게 사용될 수 있기 때문에 향후 PPF기술의 활용저변은 더욱 확대될 전망이다.

• Journal of the Microelectronics and Packaging Society
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• v.19 no.3
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• pp.1-7
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• 2012

Electroplating technology is widely used in semiconductor microelectronic industry. With the development of semiconductor integrated circuit to high density and light-small scale, Extremely high quality and plated uniformity of the deposited metals are needed. Simulation technique can help to obtain better plating results. Although a few plating simulation softwares have been commercialized, plating simulation is not widely prevalent in Korea. In this paper, principle of electroplating and mathematical modeling of plating simulation are discussed. Also introduced are some cases enhancing plating thickness uniformity on leadframe, PCB and wafer by using plating simulation.

• Journal of the Microelectronics and Packaging Society
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• v.7 no.4
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• pp.31-35
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• 2000

The stress state developed in a thin adhesive layer bonded between the semiconductor chip and the leadframe and subjected to a shear loading is investigated. The boundary element method (BEM) is employed to investigate the behavior of interface stresses. Within the context of a linear elastic theory, a stress singularity of type $\gamma^{\lambda=1}$(0<1<1) exists at the point where the interface between one of the rigid adherends and the adhesive layer intersects the free surface. Such singularity might lead to edge crack or delamination.

• Design & Manufacturing
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• v.6 no.1
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• pp.95-100
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• 2012

In this study, a novel Cu composite sheet with embedded high electric conduction path was developed as another alternative for the interconnect materials possessing high electrical conductivity as well as high strength. The Cu composite sheet was fabricated by forming Ag conduction paths not within the interior but on the surface of a high strength Cu substrate by damascene electroplating process. As a result, the electrical conductivity increased by 40% thanks to mesh type Ag conduction paths, while the ultimate tensile strength decreased by 20%. The interfacial fracture resistance of Cu composite sheet prepared by damascene electroplating increased by above 50 times compared to Cu composite sheet by conventional electroplating. For feasibility test for practical application, a leadframe for LED module was manufactured by a progressive blanking and piercing processes, and the blanked surface profile was evaluated as a function of the volume fraction of Ag conduction paths. As Ag conduction path became finer, pressing formability improved.

• Journal of the Korean Society for Precision Engineering
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• v.18 no.5
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• pp.147-156
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• 2001

본 연구에서는 칩 캡슐화 성형 공정 중의 패들 변형을 해석하기 위한 방법론이 연구되었다. 헬레쇼오 근사 모델에 근거한 유한요소법이 칩 캐비티에서의 유동 해석을 위해 사용되었다. 리드 프레임 상의 구멍을 통한 통과 유동해석을 위한 근사모델이 제안되었다. 본 연구에서 제시된 해석모델에 의해 계산된 값과 실험 값은 잘 일치하였다. 유동해석을 통하여 리드프레임과 패들에 의해 경계를 이루고 있는 상, 하 캐비티간의 압력차가 계산되었다. 최종적으로 패들 변형이 압력차 계산 값을 이용하여 계산되게 된다.