• 제목/요약/키워드: layout verification method

검색결과 22건 처리시간 0.024초

LAYOUT VERIFICATION METHOD FOR DESIGNING AND MANUFACTURING OF LCOS/AM OLED MICRODISPLAY BACKPLANES

  • Smirnov, A.G.;Koukharenko, S.N.;Volk, S.V.;Zayats, A.M.
    • 한국정보디스플레이학회:학술대회논문집
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    • 한국정보디스플레이학회 2006년도 6th International Meeting on Information Display
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    • pp.112-116
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    • 2006
  • In this presentation we will describe two core elements, which combination gives a new approach to layout verification; they are a computational algorithm for modeling of photolithographical processes and a method for physical layout verification that uses output contours of that algorithm. Utilization of this approach allows to improve the quality of LCOS/AM OLED backplanes physical verification, because it considers discrepancies between mask features and printed contours on a wafer.

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마스크 아트웍 처리 및 레이아웃 검증을 위한 다각형 정형 알고리즘 (Polygon Resizing Algorithm for Mask Artwork Processing and Layout Verification)

  • 정자춘;이철동;유영욱
    • 대한전자공학회논문지
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    • 제24권6호
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    • pp.1087-1094
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    • 1987
  • In this paper, we describe about polygon resizing porblem where the given polygons are expanded or shrunk in two dimensional plane. First, the definition of polygon resizing and it's problems are given, then the enhanced XY method is proposed: the polygon resizing can be completed in one directional sweep of plane only, usisng enhanced plane sweep method. The time complexity is 0(n log n), and space complexity 0(\ulcorner), where n is the number of verties of polygons. The applications of polygon resizing to the mask artwork processing and layout verification are discussed.

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안티퓨즈 FPGA의 배선지연시간을 고려한 VHDL 모델링 (VHDL modeling considering routing delay in antifuse-based FPGAs)

  • 백영숙;조한진;박인학;김경수
    • 전자공학회논문지A
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    • 제33A권5호
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    • pp.180-187
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    • 1996
  • This paper describes a post-layout simulation method using VHDL and C for verifying the architecture of antifuse-based FPGAs and the dedicated CAD system. An antifuse-based FPGA consists of programming circuitry including decoding logic, logic modules, segmented tracks, antifuses and I/O pads. The VHDL model which includes all these elements is used for logic verification and programming verification of the implemented circuit by reconstructing the logic circuit from the bit-stream generated from layout tool. The implemented circuit comprises of logic modules and routing networks. Since the routing delay of the complex networks is comparable to the delay of the logic module in the FPGA, the accurate post-layout simulation is essential to the FPGA system. In this paper, the C program calculates the delay of the routing netowrks using SPICE, elmore or horowitz delay models and the results feedback to the VHDL simulation. Critical path anc be found from this post-layout simulation results.

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레저보트 생산공정정보 기반의 공장 레이아웃 설계 시스템 개발 (Development of a Factory Layout Design System using Leisure-Boat Building Process)

  • 이동건;정용국;신종계
    • 대한조선학회논문집
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    • 제50권1호
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    • pp.14-24
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    • 2013
  • The marine leisure industry in Korea has been the focus of the power of economic growth and the creation of jobs in recent years. In this regard, many studies concerning marine leisure are on-going in various fields. In this paper, developed a layout system and algorithm can resolve the factory and facility layout problem. For a layout design of leisure-boat factories, the leisure-boat production process is analyzed in order to derive standard production space elements for the layout of the factory. Based on the results, a draft design of the factory layout is carried out based on the manpower planning data, as well as the characteristics and relationships of each process data. A layout design of this paper can be verified through a factory simulation solution and we suggest the verification method using a SBD(simulation based design) methodology. The layout system takes into account the user's accessibility and extendibility, so it is web-oriented and uses RIA (rich Internet Application) technology. Furthermore, the system and layout algorithm of this paper are verified with samples data that show the efficient factory arrangement and practical application method.

논리회로 상호간의 연결도 검증 (Verification of Logic Gate Interconnection)

  • 정자춘;경종민
    • 대한전자공학회논문지
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    • 제24권2호
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    • pp.338-346
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    • 1987
  • This paper describes a method for verifying whether a given geometrical layout correcdtly reflects the original logic level description. The logic description extracted from layout data was directly compadred with the original logic diagram generated at logic level design stage where the logic diagram is represented as a weighted multi-place graph. The comparison is based on graph isomorphism and error messages(error categories and locations)are invoked if any difference is found between the two logic descriptions. An efficient partitioning algorithm which consists of two steps, candidate selection and equal weight partitioning procedure, enables the entire verification process to occur in O(n log n) time.

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웹 환경 하에서의 제약 만족 기법에 의한 공간 계획 시스템 (A Web-based Spatial Layout Planning System with Constraint Satisfaction Problems)

  • 정재은;전승범;조근식
    • 한국정보과학회논문지:컴퓨팅의 실제 및 레터
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    • 제6권2호
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    • pp.216-224
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    • 2000
  • 공간 계획 시스템(Spatial Layout Planning System)은 사용자의 요구에 따라 사각의 자원을 일정 공간 안에 할당하고 사용자의 만족도를 최대화함으로써 공간 효율성을 최적화하는 시스템이다. 공간 계획 문제는 방대한 범위의 공간을 탐색해야 하므로 시간과 공간적 측면에서 높은 복잡도(Complexity)를 갖는 문제이다. 또한 특정 영역의 수정 요구나 재설계 요구와 같은 사용자의 동적인 요구 사항들을 수용할 수도 있어야 한다. 본 논문에서는 CSP(Constraint Satisfaction Problems) 해결 기법 기반의 자원 할당법을 이용함으로써 효과적으로 공간 계획 문제를 해결할 수 있도록 하였으며 사용자의 요구에 따라 변화되는 제약조건은 지능형 사용자 인터페이스 모델을 통해 좀 더 향상된 결과가 도출될 수 있도록 설계 및 구현하였다. 또한, 2차원 도면에서의 수정 요구에 대한 편이성과 시각적 검증을 위해 웹 환경 하에서의 VRML(Virtual Reality Modeling Language)을 이용한 3차원 도면을 보여준다.

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복잡한 다층 RLC 배선구조에서의 TWA를 기반으로 한 효율적인 시그널 인테그러티 검증 (A New TWA-Based Efficient Signal Integrity Verification Technique for Complicated Multi-Layer RLC Interconnect Lines)

  • 조찬민;어영선
    • 대한전자공학회논문지SD
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    • 제43권7호
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    • pp.20-28
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    • 2006
  • 본 논문에서는 불규칙하고 복잡한 다층(multi-layer) RLC 배선에 대하여 TWA(Traveling-wave-based Waveform Approximation)을 기반으로 한 새로운 시그널 인테그러티 검증에 대한 방법을 제시한다. 실제 레이아웃 구조의 불규칙한 배선을 가상 직선 배선으로 변환하고 이를 TWA 기법을 사용하여 효율적으로 검증하였다. 여기서 제안된 방법은 3차원 구조에 대한 회로 모델을 사용한 일반적인 SPICE 시뮬레이션에 비하여 계산시간을 현저하게 단축시킬 수 있으며, 타이밍의 경우 5% 이내에서, 크로스톡의 경우 10% 이내에서 정확하다는 것을 보인다.

수중강판의 결함 및 열화 검출을 위한 탄성파 유한요소 시뮬레이션 (Finite Element Simulation of Elastic Waves for Detecting Defects and Deteriorations in Underwater Steel Plates)

  • 우진호;나원배
    • 한국해양공학회지
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    • 제27권3호
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    • pp.61-66
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    • 2013
  • This paper presents the results of finite element simulations of elastic wave propagation in an underwater steel plate and the verification of a proposed method utilizing elastic wave-based damage detection. For the simulation and verification, we carried out the following procedures. First, three-dimensional finite element models were constructed using a general purpose finite element program. Second, two types of damages (mechanical defects and deteriorations) were applied to the underwater steel plate and three parameters (defect location, defect width, and depth) were considered to adjust the severity of the applied damages. Third, elastic waves were generated using the oblique incident method with a Gaussian tone burst, and the response signals were obtained at the receiving point for each defect or deterioration case. In addition, the received time domain signals were analyzed, particularly by measuring the magnitudes of the maximum amplitudes. Finally, the presence and severity of each type of damage were identified by the decreasing ratios of the maximum amplitudes. The results showed that the received signals for the models had the same global pattern with minor changes in the amplitudes and phases, and the decreasing ratio generally increased as the damage area increased. In addition, we found that the defect depth was more critical than the width in the decrease of the amplitude. This mainly occurred because the layout of the depth interfered with the elastic wave propagation in a more severe manner than the layout of the width. An inverse analysis showed that the proposed method is applicable for detecting mechanical defects and quantifying their severity.

해양플랜트 소형 유틸리티장비의 FEED 검증 프로세스에 대한 연구 (A Study of FEED Verification process of Small Utility Equipment in Offshore plant)

  • 한성종;박범
    • 플랜트 저널
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    • 제13권2호
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    • pp.39-45
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    • 2017
  • 본 논문은 시스템엔지니어링기법을 이용하여 해양플랜트 산업의 소형 유틸리티 장비의 입찰단계에서 사용가능한 FEED 검증 수행모델에 대한 연구이다. 현재 국내 해양플랜트 기자재산업계는 해양플랜트에 진출하면서 프로젝트 수행에 따른 재정적 위험에 직면한 상태이며, 그 주요한 원인으로 기자재업체의 발주처(COMPANY 또는 EPC: Engineering, Procurement and Construction) 로부터 제공받은 FEED 결과물에 대한 검증능력부족으로 조사되었다. 이에 요구사항 분석, 기능, 성능분석 및 물리적아키텍처 구축프로세스를 순차적으로 적용하는 시스템 엔지니어링 기법을 간략화 한 FEED 설계 검증방법을 제안하고 이를 소형 유틸리티 장비(Air Compressor)를 대상으로 기존의 경험에 의존한 검증방법과 개발한 FEED 검증 모델을 적용한 결과를 비교함으로써 개발된 모델의 사용적정성을 검증하였다.

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동력 분기/순환 구조를 갖는 회전기계의 정성적 성능해석 (Performance Prediction of Rotating Machinery Having Power Split/Circulaled Transmission)

  • 조한상;이동준;이장무;박영일;임원식
    • 한국정밀공학회:학술대회논문집
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    • 한국정밀공학회 1994년도 추계학술대회 논문집
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    • pp.953-957
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    • 1994
  • A performance prediction method is presented in this paper for design of a rotating machinery having power split/circulated transmisson with slip elements and planetary gears. And internal power flow patterns of such systems are theoretically analyzed by using mathematical modeling. To estimate usefulness of the designed machinary, geometrical approach has been adopted through the performance locus diagram which represents overall characteristics of the system. This gives us complect prediction of the qualitative performane and effects of design factors such as system layout, types and gear ratios of planetary gears and disign parameters of slip elements. The results for one of them are compared with experimental ones using dynamometer for verification.

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