• 한국정보디스플레이학회:학술대회논문집
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• 2006.08a
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• pp.112-116
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• 2006

In this presentation we will describe two core elements, which combination gives a new approach to layout verification; they are a computational algorithm for modeling of photolithographical processes and a method for physical layout verification that uses output contours of that algorithm. Utilization of this approach allows to improve the quality of LCOS/AM OLED backplanes physical verification, because it considers discrepancies between mask features and printed contours on a wafer.

• Journal of the Korean Institute of Telematics and Electronics
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• v.24 no.6
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• pp.1087-1094
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• 1987

In this paper, we describe about polygon resizing porblem where the given polygons are expanded or shrunk in two dimensional plane. First, the definition of polygon resizing and it's problems are given, then the enhanced XY method is proposed: the polygon resizing can be completed in one directional sweep of plane only, usisng enhanced plane sweep method. The time complexity is 0(n log n), and space complexity 0(\ulcorner), where n is the number of verties of polygons. The applications of polygon resizing to the mask artwork processing and layout verification are discussed.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.5
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• pp.180-187
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• 1996

This paper describes a post-layout simulation method using VHDL and C for verifying the architecture of antifuse-based FPGAs and the dedicated CAD system. An antifuse-based FPGA consists of programming circuitry including decoding logic, logic modules, segmented tracks, antifuses and I/O pads. The VHDL model which includes all these elements is used for logic verification and programming verification of the implemented circuit by reconstructing the logic circuit from the bit-stream generated from layout tool. The implemented circuit comprises of logic modules and routing networks. Since the routing delay of the complex networks is comparable to the delay of the logic module in the FPGA, the accurate post-layout simulation is essential to the FPGA system. In this paper, the C program calculates the delay of the routing netowrks using SPICE, elmore or horowitz delay models and the results feedback to the VHDL simulation. Critical path anc be found from this post-layout simulation results.

• Journal of the Society of Naval Architects of Korea
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• v.50 no.1
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• pp.14-24
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• 2013

The marine leisure industry in Korea has been the focus of the power of economic growth and the creation of jobs in recent years. In this regard, many studies concerning marine leisure are on-going in various fields. In this paper, developed a layout system and algorithm can resolve the factory and facility layout problem. For a layout design of leisure-boat factories, the leisure-boat production process is analyzed in order to derive standard production space elements for the layout of the factory. Based on the results, a draft design of the factory layout is carried out based on the manpower planning data, as well as the characteristics and relationships of each process data. A layout design of this paper can be verified through a factory simulation solution and we suggest the verification method using a SBD(simulation based design) methodology. The layout system takes into account the user's accessibility and extendibility, so it is web-oriented and uses RIA (rich Internet Application) technology. Furthermore, the system and layout algorithm of this paper are verified with samples data that show the efficient factory arrangement and practical application method.

• Journal of the Korean Institute of Telematics and Electronics
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• v.24 no.2
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• pp.338-346
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• 1987

This paper describes a method for verifying whether a given geometrical layout correcdtly reflects the original logic level description. The logic description extracted from layout data was directly compadred with the original logic diagram generated at logic level design stage where the logic diagram is represented as a weighted multi-place graph. The comparison is based on graph isomorphism and error messages(error categories and locations)are invoked if any difference is found between the two logic descriptions. An efficient partitioning algorithm which consists of two steps, candidate selection and equal weight partitioning procedure, enables the entire verification process to occur in O(n log n) time.

• Journal of KIISE:Computing Practices and Letters
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• v.6 no.2
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• pp.216-224
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• 2000

The spatial layout planning system allocates rectangular resources in the limited space according to user requirements, This system also can optimizes the spatial allocation problem to maximize the user's requirement. The spatial layout planning Problems for this system can be solved by searching a wide area of space since this problem entails the non-polynomial algorithm. By accommodating the user's dynamic requirements, the modification of a specific space and the redesign of the whole area can be accomplished. In this paper, the spatial layout planning problem is solved efficiently with a resource allocation method based on CSP. The dynamic constraints by adding user requirements are accommodated through the intelligent user Interface. The 3-D layout on the web environment by using VRML is also shown for providing for the visual verification of the 2-D layout and, thereafter, the additional modification of the 2-D layout.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.7 s.349
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• pp.20-28
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• 2006

A new TWA(Traveling-wave-based Waveform Approximation)-based signal integrity verification method for practical interconnect layout structures which are composed of non-uniform RLC lines with various discontinuities is presented. Transforming the non-uniform lines into virtual uniform lines, signal integrity of the practical layout structures can be very efficiently estimated by using the TWA-technique. It is shown that the proposed technique can estimate the signal integrity much more efficiently than generic SPICE circuit model with 5% timing error and 10% crosstalk error.

• Journal of Ocean Engineering and Technology
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• v.27 no.3
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• pp.61-66
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• 2013

This paper presents the results of finite element simulations of elastic wave propagation in an underwater steel plate and the verification of a proposed method utilizing elastic wave-based damage detection. For the simulation and verification, we carried out the following procedures. First, three-dimensional finite element models were constructed using a general purpose finite element program. Second, two types of damages (mechanical defects and deteriorations) were applied to the underwater steel plate and three parameters (defect location, defect width, and depth) were considered to adjust the severity of the applied damages. Third, elastic waves were generated using the oblique incident method with a Gaussian tone burst, and the response signals were obtained at the receiving point for each defect or deterioration case. In addition, the received time domain signals were analyzed, particularly by measuring the magnitudes of the maximum amplitudes. Finally, the presence and severity of each type of damage were identified by the decreasing ratios of the maximum amplitudes. The results showed that the received signals for the models had the same global pattern with minor changes in the amplitudes and phases, and the decreasing ratio generally increased as the damage area increased. In addition, we found that the defect depth was more critical than the width in the decrease of the amplitude. This mainly occurred because the layout of the depth interfered with the elastic wave propagation in a more severe manner than the layout of the width. An inverse analysis showed that the proposed method is applicable for detecting mechanical defects and quantifying their severity.

• Plant Journal
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• v.13 no.2
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• pp.39-45
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• 2017

This paper is a study on FEED validation model that can be used in the bidding stage of small utility equipment in offshore plant industry using system engineering technique. Currently, domestic marine plant equipment industry companies are faced with the financial risk of project execution as they enter marine plant. The major cause was the insufficient ability to verify the FEED output from the contractor (Engineering or Procurement and Construction) of the equipment manufacturer (COMPANY or EPC). Therefore, we propose FEED design verification method that simplifies the system engineering method that sequentially applies requirements analysis, function, performance analysis and physical architecture building process. Also, we verified the suitability of the developed model by comparing the results of applying the developed FEED verification model and the verification method that depends on the existing experience for the small utility equipment (Air Compressor).

• Proceedings of the Korean Society of Precision Engineering Conference
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• 1994.10a
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• pp.953-957
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• 1994

A performance prediction method is presented in this paper for design of a rotating machinery having power split/circulated transmisson with slip elements and planetary gears. And internal power flow patterns of such systems are theoretically analyzed by using mathematical modeling. To estimate usefulness of the designed machinary, geometrical approach has been adopted through the performance locus diagram which represents overall characteristics of the system. This gives us complect prediction of the qualitative performane and effects of design factors such as system layout, types and gear ratios of planetary gears and disign parameters of slip elements. The results for one of them are compared with experimental ones using dynamometer for verification.