• Title/Summary/Keyword: layer 2C

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Effects of iron atom, substrate on two-dimensional C2N crystals

  • Noh, Min Jong;Kim, Yong Hoon
    • Proceeding of EDISON Challenge
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    • 2016.03a
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    • pp.288-291
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    • 2016
  • Recently, there has been a lot of researches related to two-dimensional (2D) materials due to their new properties and applications emerging upon 2D confinement. A new type of graphene like two-dimensional layer material, nitrogenated holey two-dimensional structure C2N-h2D, that is possession of evenly distributed holes and nitrogen atoms with proper bandgap has been synthesized. Previous calculation studies already have shown that the variance of the orbital interaction, band structure of few-layer C2N-h2D suggests that interlayer coupling does play an important role in its electronic properties. In this point, using first-principles density functional theory calculation, we here explore the effect of porous embedded iron atom and iron substrate on encapsulated few layer C2N-h2D. We show the atomic structures and the corresponding electronic structures of Fe@C2N to elucidate the effect of iron. Finally, this study demonstrates that embedded iron C2N has AA-stacking as most favorable stacked structure in contrast to pure C2N. In addition, iron substrate modifies its encapsulated C2N from semi-metallic states to metallic state.

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Characterization of Sol-gel Coated Pb(ZrTi)O3 Thin film for Piezoelectric Vibration MEMS Energy Harvester (압전 MEMS 진동에너지 수집소자를 위한 졸겔 공법기반의 Pb(ZrTi)O3 박막의 특성 분석 및 평가)

  • Park, Jong-C.;Park, Jae-Y.
    • Proceedings of the KIEE Conference
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    • 2009.07a
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    • pp.1240_1241
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    • 2009
  • In this paper, sol-gel-spin coated $Pb(ZrTi)O_3$ thin film with $ZrO_2$ buffer-layer and $PbTiO_3$ seed-layer was investigated for vibration MEMS energy harvester to scavenge power from ambient vibration via d33 piezoelectric mode. Piezoelectric thin film deposition techniques on insulating layer is the important key for $d_{33}$ mode of piezoelectric vibration energy harvester. $ZrO_2$ buff-layer was utilized as an insulating layer. $PbTIO_3$ seed-layer was applied as an inter-layer between PZT and $ZrO_2$ layer to improve the crystalline of PZT thin film. The fabricated PZT thin film had a remanent polarization of 5.3uC/$cm^2$ and the coercive field of 60kV/cm. The fabricated energy harvester using PZT thin film with PTO seed-layer generated 1.1uW of electrical power to $2.2M{\Omega}$ of load with $4.4V_{pvp}$ from vibration of 0.39g at 528Hz.

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반도체 검출기의 절연 최적화를 위한 다층 절연막 평가

  • Park, Jeong-Eun;Myeong, Ju-Yeon;Kim, Dae-Guk;Kim, Jin-Seon;Sin, Jeong-Uk;Gang, Sang-Sik;Nam, Sang-Hui
    • Proceedings of the Korean Vacuum Society Conference
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    • 2014.02a
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    • pp.372-372
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    • 2014
  • 반도체 검출기는 입사되는 X선 에너지에 의하여 이온화되어 발생하는 전자 전공쌍을 수집함으로 방사선 정보를 확인하는 선량계로써 많은 연구와 활용이 이루어지고 있다. 하지만, X선 에너지에 의하여 반도체 검출기에서 발생하는 전기적 신호량이 높지 않기 때문에 누설 전류의 저감이 필수적이다. 누설 전류를 저감시키기 위한 방안으로 반도체 층과 전극 층의 Schottky Contact 구조의 설계, Insulating Layer의 사용, 높은 비저항의 반도체 물질 연구 등이 이루어지고 있다. 하지만, 기존에 누설 전류 저감을 위하여 Insulating Layer를 전극층과 반도체 층 사이에 형성하는 연구에 있어서 Insulating Layer와 반도체 층의 계면 사이에서 발생하는 Charge Trapping으로 인하여 생성되는 신호의 Reproducibility 저하, 동영상 적용의 제한 등의 문제점을 겪어왔다. 이에 본 논문에서는 누설 전류를 저감시킴과 동시에 Charge Trapping의 최소화를 이루기 위하여 Insulating Layer의 두께 최적화 연구를 수행하였다. 본 연구에서 사용한 Insulating Layer는 검출기 표면에 입사하는 X선 정보 손실을 최소화 시키는 동시에 누설 전류와 Charge Trapping을 최소화 시키는 방법으로써 CVD방법으로 검출기 표면에 균일하게 Insulating Layer를 코팅하였다. Insulating 물질은 Parylene을 사용하였으며, 그 중 온도, 습도 등 외부환경에 영향을 적게 받는 type C를 사용하였다. 증착에 사용한 장비의 진공도는 Torr로 설정하여 증착되는 Parylene의 두께가 약 $0.3{\mu}m$가 되게 하였으며, 실험에는 반도체 물질 PbO를 사용하였다. Parylene의 절연 특성은 Dark Current와 Sensitivity를 측정한 SNR을 이용하여 Parylene코팅이 되지 않은 동일 반도체 검출기와의 신호를 비교하였으며 또한 Parylene를 다층 제작한 검출기의 수집 신호량을 비교하였다. 제작한 검출기의 X선 조사 시의 수집 전하량 측정 결과, 100 kVp, 100mA, 0.03s의 X선 조건에서 $1V/{\mu}m$의 기준 시, Parylene를 코팅하지 않은 PbO 검출기의 Dark current는 0.0501 nA/cm2, Sensitivity는 0.6422 nC/mR-cm2, SNR은 12.184이었으며, Parylene단층의 두께인 $0.3{\mu}m$로 증착된 시편의 Dark current는 0.04097 nA/cm2, Sensitivity는 0.53732 nC/mR-cm2으로 Dark current가 감소되고 sensitivity도 감소하였지만 SNR은 13.1150으로 높아진 것을 확인할 수 있었다. Perylene이 $0.6{\mu}m$로 증착된 시편의 경우, Dark Current는 0.04064 nA/cm2, Sensitivity는 0.31473 nC/mR-cm2, SNR은 7.7443으로써 Insulating Layer가 없는 시편보다 SNR이 약 40% 낮아진 것을 확인할 수 있었다. Parylene이 $0.9{\mu}m$로 증착된 시편의 경우 Dark current는 0.0378 nA/cm2, Sensitivity 0.0461 nC/mR-cm2로 Insulating Layer가 없는 시편에 비해 SNR은 약 1/12배 감소한 1.2196이었고, Parylene이 $1.2{\mu}m$로 증착된 시편의 SNR은 1.1252로서 더 감소하였다. 따라서 Parylene을 다층 코팅한 검출기일수록 절연 효과의 영향이 커짐으로써 SNR 비교 시 수집되는 신호량이 줄어드는 것을 확인하였다. 반도체 검출기의 누설 전류를 저감시킴과 동시에 신호 수집율에 영향을 최소화시키기 위하여 Insulating Layer의 두께를 적절하게 설정하여 적용하면 Insulating Layer가 없는 검출기에 비해 누설전류를 최소한으로 줄일 수 있고 신호 검출효율이 감소하는 것을 방지할 수 있을 것이라 사료된다.

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Effect of $Al_2O_3$ pre-layers formed using protective Si-oxide layer on the growth of ultra thin ${\gamma}-Al_2O_3$ epitaxial layer (보호용 실리콘 산화막을 이용하여 제조된 $Al_2O_3$ 예비층이 초박막 ${\gamma}-Al_2O_3$ 에피텍시의 성장에 미치는 영향)

  • Jung, Young-Chul;Jun, Bon-Keun;Ishida, Makoto
    • Journal of Sensor Science and Technology
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    • v.9 no.5
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    • pp.389-395
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    • 2000
  • In this paper, we propose the formation of an $Al_2O_3$ pre-layer using a protective Si-oxide layer and Al layer. Deposition of a thin film layer of aluminum onto a Si surface covered with a thin Si-oxide layer and annealing at $800^{\circ}C$ led to the growth of epitaxial $Al_2O_3$ layer on Si(111). And ${\gamma}-Al_2O_3$ layer was grown on the $Al_2O_3$ per-layer. Etching of the Si substrate by $N_2O$ gas could be avoided in the initial growth stage by the $Al_2O_3$ pre-layer. It was confirmed that the $Al_2O_3$ pre-layer was effective in improving the surface morphology of the very thin ${\gamma}-Al_2O_3$ films.

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Electrical Characteristics of Organic Thin Film Transistors with Dual Layer Insulator on Plastic Substrates (이중 절연막 구조를 가전 플라스틱 유기 박막트랜지스터의 전기적 특성)

  • 최승진;이인규;박성규;김원근;문대규
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2002.07a
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    • pp.194-197
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    • 2002
  • Applying dual layer insulator on plastic substrates improved electrical characteristics of organic thin film transistor(TFT). A high-quality silicon dioxide(SiO$_2$) suitable for a insulator was deposited on plastic substrates by e-beam evaporation at 110$^{\circ}C$. The insulator film which was treated by N$_2$ annealing at 150$^{\circ}C$ showed excellent I-V, C-V characteristics. The dual layer insulator structure of polyimide-SiO$_2$ improved the roughness of SiO$_2$ surface and showed very low leakage current. In addition, the flat band voltage has been reduced from -2.5V to about 0.5V.

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TiN and TiC Gas Alloying of Ti-6Al-4V Alloy by CO2 Laser (CO2 레이저를 이용한 Ti-6Al-4V합금의 TiN 및 TiC 가스 합금화)

  • Song, K.H.;Lee, O.Y.
    • Journal of the Korean Society for Heat Treatment
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    • v.9 no.3
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    • pp.177-186
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    • 1996
  • Surface alloying of Ti alloy by $CO_2$ laser is able to produce few hundred micrometers thick TiN or TiC surface-alloyed layer with high hardness on the substrate by injecting reaction gas($N_2$ or $CH_4$). Laser surface alloying by means of process control is in many applications essential in order to obtain predictable hardening layer. This research has been investigated the effect of such parameters on TiN and TiC gas alloying of Ti-6Al-4V alloy by $CO_2$ laser. The maximum surface hardness of TiN layer was obtained 1750Hv on the conditions of 0.8kW laser power, 0.8m/min scanning speed and 100% $N_2$ atmosphere. However, the maximum hardness of TiC formation layer after laser treatment was about 630Hv. As scanning speed was increased, the hardness and depth of these layers were decreased at constant laser power.

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Double Layer (Wet/CVD $SiO_2$)의 Interface Trap Density에 대한 연구

  • Lee, Gyeong-Su;Choe, Seong-Ho;Choe, Byeong-Deok
    • Proceedings of the Korean Vacuum Society Conference
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    • 2012.02a
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    • pp.340-340
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    • 2012
  • 최근 MOS 소자들이 게이트 산화막을 Mono-layer가 아닌 Multi-Layer을 사용하는 추세이다. Bulk와 High-k물질간의 Dangling Bond를 줄이기 위해 Passivation 층을 만드는 것을 예로 들 수 있다. 이러한 Double Layer의 쓰임이 많아지면서 계면에서의 Interface State Density의 영향도 커지게 되면서 이를 측정하는 방법에 대한 연구가 활발히 진행되고 있다. 본 연구에서는 $SiO_2$ Double Layer의 Interface State Density를 Conductance Method를 사용하여 구하는 연구를 진행하였다. Wet Oxidation과 Chemical Vapor Deposition (CVD) 공정을 이용하여 $SiO_2$ Double-layer로 증착한 후 Aluminium을 전극으로 하는 MOS-Cap 구조를 만들었다. 마지막 공정은 $450^{\circ}C$에서 30분 동안 Forming-Gas Annealing (FGA) 공정을 진행하였다. LCR meter를 이용하여 high frequency C-V를 측정한 후 North Carolina State University California Virtual Campus (NCSU CVC) 프로그램을 이용하여 Flatband Voltage를 구한 후에 Conductance Method를 측정하여 Dit를 측정하였다. 본 연구 결과 Double layer (Wet/CVD $SiO_2$)에 대해서 Conductance Method를 방법을 이용하여 Dit를 측정하는 것이 유효하다는 것을 확인 할 수 있었다. 본 실험은 앞으로 많이 쓰이고 측정될 Double layer (Wet/CVD $SiO_2$)에 대한 Interface State Density의 측정과 분석에 대한 방향을 제시하는데 도움이 될 것이라 판단된다.

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Optimization of μc-SiGe:H Layer for a Bottom Cell Application

  • Jo, Jae-Hyeon;Lee, Jun-Sin
    • Proceedings of the Korean Vacuum Society Conference
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    • 2014.02a
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    • pp.322.1-322.1
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    • 2014
  • Many research groups have studied tandem or multi-junction cells to overcome this low efficiency and degradation. In multi-junction cells, band-gap engineering of each absorb layer is needed to absorb the light at various wavelengths efficiently. Various absorption layers can be formed using multi-junctions, such as hydrogenated amorphous silicon carbide (a-SiC:H), amorphous silicon germanium (a-SiGe:H) and microcrystalline silicon (${\mu}c$-Si:H), etc. Among them, ${\mu}c$-Si:H is the bottom absorber material because it has a low band-gap and does not exhibit light-induced degradation like amorphous silicon. Nevertheless, ${\mu}c$-Si:H requires a much thicker material (>2 mm) to absorb sufficient light due to its smaller light absorption coefficient, highlighting the need for a high growth rate for productivity. ${\mu}c$-SiGe:H has a much higher absorption coefficient than ${\mu}c$-Si:H at the low energy wavelength, meaning that the thickness of the absorption layer can be decreased to less than half that of ${\mu}c$-Si:H. ${\mu}c$-SiGe:H films were prepared using 40 MHz very high frequency PECVD method at 1 Torr. SiH4 and GeH4 were used as a reactive gas and H2 was used as a dilution gas. In this study, the ${\mu}c$-SiGe:H layer for triple solar cells applications was performed to optimize the film properties.

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Electrical and Material Characteristics of HfO2 Film in HfO2/Hf/Si MOS Structure (HfO2/Hf/Si MOS 구조에서 나타나는 HfO2 박막의 물성 및 전기적 특성)

  • Bae, Kun-Ho;Do, Seung-Woo;Lee, Jae-Sung;Lee, Yong-Hyun
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.22 no.2
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    • pp.101-106
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    • 2009
  • In this paper, Thin films of $HfO_2$/Hf were deposited on p-type wafer by Atomic Layer Deposition (ALD). We studied the electrical and material characteristics of $HfO_2$/Hf/Si MOS capacitor depending on thickness of Hf metal layer. $HfO_2$ films were deposited using TEMAH and $O_3$ at $350^{\circ}C$. Samples were then annealed using furnace heating to $500^{\circ}C$. Round-type MOS capacitors have been fabricated on Si substrates with $2000\;{\AA}$-thick Pt top electrodes. The composition rate of the dielectric material was analyzed using TEM (Transmission Electron Microscopy), XRD (X-ray Diffraction) and XPS (X-ray Photoelectron Spectroscopy). Also the capacitance-voltage (C-V), conductance-voltage (G-V), and current-voltage (I-V) characteristics were measured. We calculated the density of oxide trap charges and interface trap charges in our MOS device. At the interface between $HfO_2$ and Si, both Hf-Si and Hf-Si-O bonds were observed, instead of Si-O bond. The sandwiched Hf metal layer suppressed the growing of $SiO_x$ layer so that $HfSi_xO_y$ layer was achieved. And finally, the generation of both oxide trap charge and interface trap charge in $HfO_2$ film was reduced effectively by using Hf metal layer.

The Effects of Processing Parameters on Surface Hardening Layer Characteristics of Low Temperature Plasma Nitriding of 316L Austenitic Stainless Steel (316L 오스테나이트계 스테인리스강의 저온 플라즈마질화처리시 공정변수가 표면경화층 특성에 미치는 영향)

  • Lee, Insup
    • Journal of the Korean institute of surface engineering
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    • v.52 no.4
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    • pp.194-202
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    • 2019
  • A systematic investigation was made on the influence of processing parameters such as gas composition and treatment temperature on the surface characteristics of hardened layers of low temperature plasma nitrided 316L Austenitic Stainless Steel. Various nitriding processes were conducted by changing temperature ($370^{\circ}C$ to $430^{\circ}C$) and changing $N_2$ percentage (10% to 25%) for 15 hours in the glow discharge environment of a gas mixture of $N_2$ and $H_2$ in a plasma nitriding system. In this process a constant pressure of 4 Torr was maintained. Increasing nitriding temperature from $370^{\circ}C$ to $430^{\circ}C$, increases the thickness of S phase layer and the surface hardness, and also makes an improvement in corrosion resistance, irrespective of nitrogen percent. On the other hand, increasing nitrogen percent from 10% to 25% at $430^{\circ}C$ decreases corrosion resistance although it increases the surface hardness and the thickness of S phase layer. Therefore, optimized condition was selected as nitriding temperature of $430^{\circ}C$ with 10% nitrogen, as at this condition, the treated sample showed better corrosion resistance. Moreover to further increase the thickness of S phase layer and surface hardness without compromising the corrosion behavior, further research was conducted by fixing the $N_2$ content at 10% with introducing various amount of $CH_4$ content from 0% to 5% in the nitriding atmosphere. The best treatment condition was determined as 10% $N_2$ and 5% $CH_4$ content at $430^{\circ}C$, where the thickness of S phase layer of about $17{\mu}m$ and a surface hardness of $980HV_{0.1}$ were obtained (before treatment $250HV_{0.1}$ hardness). This specimen also showed much higher pitting potential, i.e. better corrosion resistance, than specimens treated at different process conditions and the untreated one.