• 전자공학회논문지A
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• 제32A권8호
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• pp.64-70
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• 1995

A new DC drain-current model of GaAs MESFET with improved accuracy is proposed in this paper. The proposed model includes the decrease of current slope according to gate voltages. It is possible to represent a transconductance compression using the proposed model. It shows improved transconductance and output resistance in accuracy from the forward biased gate region to near the cutoff region. The wquaer error of saturation current is decreased by 46% compared with Statz model. The proposed model can be useful for the simulation of large-signal operation and harmonic distortion.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2003년도 International Meeting on Information Display
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• pp.72-75
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• 2003

For the analog output buffer in the data driver for large size and high resolution TFT-LCDs, we proposed operational amplifier (op-amp) which contains newly developed transconductance-boosted input stage which enables the low-power consumption and the high slew-rate. The slew-rate and the quiescent current of the proposed op-amp are $6.1V/{\mu}sec$ and $8{\mu}A$, respectively.

• Journal of Korean Vacuum Science & Technology
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• 제3권1호
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• pp.38-42
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• 1999

Using the LOCOS process, we have fabricated the lateral type polysilicon field emission triodes with poly-Si/oxide/Si structure and investigated their current-voltage characteristics for three biasing modes of operation. The fabricated devices exhibit excellent electrical performances such as a relatively low turn-on anode voltage of 14 V at VGC = 0V, a stable and high emission current of 92${\mu}$A/triode over 90 hours, a small gate leakage current of 0.23 ${\mu}$A/triode and an outstanding transconductance of 57${\mu}$S/5triodes at VGC = 5V and VAC = 26V. these superior electrical operation is believed to be due to a large field enhancement effect, which is related to the sharp cathode tips produced by the LOCOS process as well as the high aspect ratio (height /radius ) of the cathode tip end.

• 전기의세계
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• 제30권10호
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• pp.645-654
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• 1981

A technique has been proposed for fabricating a submicron channel vertical V-groove JFET using standard photolithography. A finite element numerical simulation of the V-groove JFET operation was performed using a FORTRAN progrma run on a Cyber-174 computer. The numerical simulation predicts pentode like common source output characteristics for the p$^{+}$n Vertical V-groove JFET with maximum transconductance representing approximately 6 precent of the zero bias drain conductance value and markedly high drain conductance at large drain voltages. An increase in the acceptor concentration of the V-groove JFET gate was observed to cause a significant increase in the transconductance of the device. Therefore, as above mentioned, this paper is study on the analysis of a Vertical V-groove Junction Field Effect Transistor with Finite Element Method.d.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2009년도 9th International Meeting on Information Display
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• pp.307-309
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• 2009

We have fabricated vertical-type organic transistors (static induction transistors; SITs) with built-in nano-triode arrays formed in parallel by a colloidal-lithography technique. Using this technique, we could fabricate a microstructure in a lateral direction within a large-scale organic device without relying on photolithography. The organic transistor showed low operating voltages, high current output, and large transconductance.

• 대한전자공학회논문지SD
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• 제46권1호
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• pp.92-97
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• 2009

저 전력 소모는 의료용 이식 장치에서 매우 중요한 요소가 된다. 본 논문에 제안된 이식형 심장 박동 조절기의 감지 단에 필요한 저 전력 4차 Gm-C 필터는 다단 증폭 단으로 구현 되었다. 매우 큰 시상수를 구현하기 위해서 전류 분할 및 플로팅-게이트 기법이 적용된 OTA가 사용되었다. 측정 결과, 필터는 50 dB의 SFDR을 가지며, $1.8{\mu}$, W의 전력이 소모되었다. 전원 전압은 1.5 V가 공급되었고, 코어는 $2.4\;mm{\times}1.3\;mm$의 실리콘 면적을 차지한다. 제안된 필터는 1-poly 4-metal $0.35-{\mu}m$ CMOS 공정에서 제작되었다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2006년도 추계학술대회 논문집 Vol.19
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• pp.149-150
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• 2006

A ZnO nanowire-based FET is fabricated m this study on a flexible substrate of PES. For the flat and bent flexible substrates, the current ($I_D$) versus drain-source bias voltage ($V_{DS}$) and $I_D$ versus gate voltage ($V_G$) results are compared. The flat band was Ion/Ioff ratio of ${\sim}10^7$, a transconductance of 179 nS and a mobility of ~10.104 cm2/Vs at $V_{DS}$ =1 V. Also bent to a radius curvature of 0.15cm and experienced by an approximately strain of 0.77 % are exhibited an Ion/Ioff ratio of ${\sim}10^7$, a transconductance of ~179 nS and a mobility of ${\sim}10.10 cm^2/Vs$ at $V_{DS}$ = 1V. The electrical characteristics of the FET are not changed very much. although the large strain is given on the device m the bent state.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2006년도 추계학술대회 논문집 Vol.19
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• pp.87-88
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• 2006

Recently, poly-Si TFT-LCD starts to be mass produced using excimer laser annealing (ELA) poly-Si. The main reason for this is the good quality poly-Si and large area uniformity. We report the influence of channel length and width on poly-Si TFTs performance. Transfer characteristics of p-channel poly-Si thin film transistors fabricated on polycrystalline silicon (poly-Si) thin film transistors (TFTs) with various channel lengths and widths of 2-30 ${\mu}m$ has been investigated. In this paper, we analyzed the data of p-type TFTs. We studied threshold voltage ($V_{TH}$), on/off current ratio ($I_{ON}/I_{OFF}$), saturation current ($I_{DSAT}$), and transconductance ($g_m$) of p-channel poly-Si thin film transistors with various channel lengths and widths.

• 전자공학회논문지A
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• 제29A권4호
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• pp.33-37
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• 1992

AlGaAs/GaAs quantum well delta-doped channel FET's have been successfully fabricated using by low-pressure metalorganic chemical vapor deposition(LP-MOCVD). The FET's with a gate dimension of 1.8$\mu$m $\times$ 100$\mu$m have a maximum transconductance of 190 mS/mm and a maximum current density of 425 mA/nm. The devices show extremely broad transconductances with a large voltage swing of 2.4V. The S-parameter measurements have indicated that the current gain and power gain cutoff frequencies of the device were 7 and 15 GHz, respectively. These values are among the best performance reported for GaAs based heterojunction FET's with a similar device geometry.

• 전자공학회논문지A
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• 제32A권3호
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• pp.118-123
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• 1995

We have successfully fabricated a super low noise pseudomorphic HEMT(PHEMT) device with AlGaAs/InGaAs/GaAs sturcture by using improved T-Gate which have increased a large gaet cross-sectional area about two times in comparision with those of conventional T-gate processes. The PHEMSTs with 0.15$\mu$m-long and 140$\mu$m-wide gates have eshibited a super low noise characteristics, the noise figure of 0.45dB with associated gain of 10.87dB at 12GHz. The cut-off rewuqncy of the device is 94gHz with a transconductance of 418mS/mm.