• 제목/요약/키워드: large delay

검색결과 910건 처리시간 0.031초

Tunable Composite Right/Left-Handed Delay Line with Large Group Delay for an FMCW Radar Transmitter

  • Park, Yong-Min;Ki, Dong-Wook
    • Journal of electromagnetic engineering and science
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    • 제12권2호
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    • pp.166-170
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    • 2012
  • This paper presents a tunable composite right/left-handed (CRLH) delay line for a delay line discriminator that linearizes modulated frequency sweep in a frequency modulated continuous wave (FMCW) radar transmitter. The tunable delay line consists of 8 cascaded unit cells with series varactor diodes and shunt inductors. The reverse bias voltage of the varactor diode controlled the group delay through its junction capacitance. The measured results demonstrate a group delay of 8.12 ns and an insertion loss of 4.5 dB at 250 MHz, while a control voltage can be used to adjust the group delay by approximately 15 ns. A group delay per unit cell of approximately 1 ns was obtained, which is very large when compared with previously published results. This group delay can be used effectively in FMCW radar transmitters.

Towards Achieving the Maximum Capacity in Large Mobile Wireless Networks under Delay Constraints

  • Lin, Xiaojun;Shroff, Ness B.
    • Journal of Communications and Networks
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    • 제6권4호
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    • pp.352-361
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    • 2004
  • In this paper, we study how to achieve the maximum capacity under delay constraints for large mobile wireless networks. We develop a systematic methodology for studying this problem in the asymptotic region when the number of nodes n in the network is large. We first identify a number of key parameters for a large class of scheduling schemes, and investigate the inherent tradeoffs among the capacity, the delay, and these scheduling parameters. Based on these inherent tradeoffs, we are able to compute the upper bound on the maximum per-node capacity of a large mobile wireless network under given delay constraints. Further, in the process of proving the upper bound, we are able to identify the optimal values of the key scheduling parameters. Knowing these optimal values, we can then develop scheduling schemes that achieve the upper bound up to some logarithmic factor, which suggests that our upper bound is fairly tight. We have applied this methodology to both the i.i.d. mobility model and the random way-point mobility model. In both cases, our methodology allows us to develop new scheduling schemes that can achieve larger capacity than previous proposals under the same delay constraints. In particular, for the i.i.d. mobility model, our scheme can achieve (n-1/3/log3/2 n) per-node capacity with constant delay. This demonstrates that, under the i.i.d. mobility model, mobility increases the capacity even with constant delays. Our methodology can also be extended to incorporate additional scheduling constraints.

최소 지연시간을 갖는 CMOS buffer 회로의 설계 기법 (the Design Methodology of Minimum-delay CMOS Buffer Circuits)

  • 강인엽;송민규;이병호;김원찬
    • 대한전자공학회논문지
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    • 제25권5호
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    • pp.509-521
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    • 1988
  • In the designs of integrated circuits, the buffer circuits used for driving a large capacitive load from minimum-structured logic circuit outputs have important effects upon system throughputs. Therefore it is important to optimize the buffer circuits. In this paper, the principle of designing CMOS buffer circuits which have the minimum delay and drive the given capacitive load is discussed. That is, the effects of load capacitance upon rise time, fall time, and delay of the CMOS inverter and the effects of parasitic capacitances are finely analysed to calculate the requested minimum-delay CMOS buffer condition. This is different from the method by C.A. Mead et. al.[2.3.4.]which deals with passive-load-nMOS buffers. Large channel width MOS transistor stages are necessary to drive a large capacitive load. The effects of polysilicon gate resistances of such large stages upon delay are also analysed.And, the area of buffer circuits designed by the proposed method is smaller than that of buffer circuits designed by C.A. Mead's method.

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프로그램 수준 건설사업에서 지연관리지수(Delay Management Index)를 활용한 공사지연 예방 사례연구 (A Case Study on the Prevention of Construction Delays Using the Delay Management Index in Program Level Construction Projects)

  • 유준혁;김옥규
    • 한국건축시공학회지
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    • 제21권4호
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    • pp.347-359
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    • 2021
  • 최근 건설공사는 초대형화로 단일 공사규모가 복잡해지고 천문학적인 공사비가 소요되는 프로그램 관리 형태의 성격을 지니는 사업이 등장하고 있다. 특히, 대규모 건설사업과 같이 프로그램 수준에서 관리가 절대적으로 필요한 사업은 계획된 일정 및 비용에 대한 전제적인 관리가 필요하다. 하지만 국내의 경우 구체적인 공사지연에 관한 관리기준이 부재한 현실이다. 이에 본 연구에서는 대규모, 장기간 진행되는 프로그램 수준의 대규모 건설사업을 성공적으로 수행하고 공정지연 및 부진사업을 사전에 방지하기 위한 지연관리지수(Delay Management Index, DMI)를 개발하였다. 이를 통해 대규모 복합건설 프로젝트를 대상으로 사례연구를 수행하였으며, 프로그램 수준 건설사업을 위한 지연예방체계를 구축하였다.

대역폭과 지연의 곱이 큰 네트워크를 위한 개선된 TCP 혼잡제어 메카니즘 (Enhanced TCP Congestion Control Mechanism for Networks with Large Bandwidth Delay Product)

  • 박태준;이재용;김병철
    • 대한전자공학회논문지TC
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    • 제43권3호
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    • pp.126-134
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    • 2006
  • 현재 인터넷에서 널리 사용되고 있는 TCP는 대역폭과 지연의 곱이 큰 네트워크에서 특히 초기 시동단계를 포함하여 전반적으로 효율이 낮은 문제가 있다. 본 논문은 이 문제를 해결하기 위해 지연기반 혼잡제어(DCC: Delay-based Congestion Control) 방법을 제안한다. DCC는 선형과 지수 증가구간으로 나누어진다. 선형증가 구간은 기존의 TCP 혼잡회피 기법과 유사하며, 지수증가 구간은 혼잡에 의한 지연이 없는 경우 신속한 대역 확보를 위해 사용된다. 일반 TCP에서는 slow-start와 같은 지수증가 구간에서 대역과 지연의 곱으로 결정되는 크기의 버퍼가 제공되지 않는 경우 대역이 충분함에도 불구하고 손실이 발생하여 성능을 제한할 수 있다. 따라서 DCC에서는 RTT(Round Trip Time) 상태와 예측된 버퍼크기를 이용하여 지수증가 구간의 공급초과로 인한 손실을 방지하는 메카니즘을 제안한다. 시뮬레이션 결과를 통하여 대역과 지연의 곱이 큰 네트워크에서 DCC가 TCP에서 초기 시동시간과 throughput성능을 향상시킴을 보였다.

부 스큐 지연 방식과 피드포워드 방식을 사용한 링 발진기의 대신호 해석 (A Large-Signal Analysis of a Ring Oscillator with Feed-Forward and Negative Skewed Delay)

  • 이정광;이순재;정항근
    • 전기학회논문지
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    • 제59권7호
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    • pp.1332-1339
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    • 2010
  • This paper presents a large signal analysis of ring-type oscillators with feed forward and negative skewed delay scheme. The analysis yields the frequency increase factor due to two schemes. The large signal analysis is needed, because small signal model is limited to the initial stage of oscillation[1]. For verification of the frequency increase factor, simulation were done under the same conditions for the two different types of ring oscillators, i.e., with and without feed forward and negative skewed delay scheme. Simulation results are in good agreement with predictions based on analysis.

LMI 기법을 이용한 시간지연 대규모 불확정성 선형 시스템의 강인 안정성 (Robust Stability of Uncertain Linear Large-scale Systems with Time-delay via LMI Approach)

  • 이희송;김진훈
    • 대한전기학회논문지:전력기술부문A
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    • 제48권10호
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    • pp.1287-1292
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    • 1999
  • In large-scale systems, we frequently encounter the time-delay and the uncertainty, and these should be considered in the design of controller because these are the source of the degradation of the system performance and instability of system. In this paper, we consider the robust stability of the linear large scale systems with the uncertainties and the time-delays. The considered uncertainties are both structured uncertainty and the unstructured uncertainty. Also, the considered time-delays are time-varying having finite time derivative limits. Based on the Lyapunov theorem and the linear matrix inequality(LMI) technique, we present two sufficient conditions that guarantee the robust stability of the system. The conditions are expressed as the LMI forms which can be easily checked their feasibility by using the well-known LMI control toolbox. Finally, we show by two examples that our results are less conservative than the previous results.

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통신 지연을 갖는 고차 적분기시스템의 일치 (Consensus of High-Order Integrators With a Communication Delay)

  • 이성렬
    • 전기전자학회논문지
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    • 제19권4호
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    • pp.520-525
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    • 2015
  • 본 논문은 통신 지연이 존재하는 고차적분기 시스템의 일치문제를 다룬다. 리카티 방정식 기반의 제어기법과 시간지연의 효과를 제거해주는 부가적인 설계변수를 도입함으로써 임의로 큰 통신 지연이 존재하는 경우에도 일치 문제를 해결할 수 있음을 증명한다. 또한, 단지 하나의 변수만 설계하면 되기 때문에 기존의 설계 방법에 비하여 매우 간단하고 제어기의 존재성이 통신지연의 크기에 의존하지 않는다는 장점을 가진다.

Analysis of delay compensation in real-time dynamic hybrid testing with large integration time-step

  • Zhu, Fei;Wang, Jin-Ting;Jin, Feng;Gui, Yao;Zhou, Meng-Xia
    • Smart Structures and Systems
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    • 제14권6호
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    • pp.1269-1289
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    • 2014
  • With the sub-stepping technique, the numerical analysis in real-time dynamic hybrid testing is split into the response analysis and signal generation tasks. Two target computers that operate in real-time may be assigned to implement these two tasks, respectively, for fully extending the simulation scale of the numerical substructure. In this case, the integration time-step of solving the dynamic response of the numerical substructure can be dozens of times bigger than the sampling time-step of the controller. The time delay between the real and desired feedback forces becomes more striking, which challenges the well-developed delay compensation methods in real-time dynamic hybrid testing. This paper focuses on displacement prediction and force correction for delay compensation in the real-time dynamic hybrid testing with a large integration time-step. A new displacement prediction scheme is proposed based on recently-developed explicit integration algorithms and compared with several commonly-used prediction procedures. The evaluation of its prediction accuracy is carried out theoretically, numerically and experimentally. Results indicate that the accuracy and effectiveness of the proposed prediction method are of significance.