• Proceedings of the KIEE Conference
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• 1988.07a
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• pp.282-284
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• 1988

In this paper, a method for constructing parallel-in, parallel-out multipliers in GF($2^{m}$) is presented. The proposed system is composed of two operational parts by using shift register. One is a multiplicative arithmetical operation part capable of the multiplicative arithmetic and modulo 2 operation to all product terms with the same degree. And the other is an irreducible polynomial operation part to outputs from the multiplicative arithmetical operation part. Since the total hardware is linearly m dependant to an GF($2^{m}$), this system has a reasonable merit when m increases. And also this system is suited for VLSI implementation due to simple, regular, and concurrent properties.

• Journal of the Korean Mathematical Society
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• v.43 no.3
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• pp.507-528
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• 2006

In this paper we show that the Koecher's Jordan automorphic generators of one variable on an irreducible symmetric cone are enough to determine the elements of scalar multiple of the Jordan identity on the attached simple Euclidean Jordan algebra. Its various geometric, Jordan and Lie theoretic interpretations associated to the Cartan-Hadamard metric and Cartan decomposition of the linear automorphisms group of a symmetric cone are given with validity on infinite-dimensional spin factors

• Journal of the Korean Mathematical Society
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• v.52 no.4
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• pp.853-868
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• 2015

Let G be a complex semisimple simply connected linear algebraic group. The main result of this note is to give several equivalent criteria for the untwistedness of the twisted cubes introduced by Grossberg and Karshon. In certain cases arising from representation theory, Grossberg and Karshon obtained a Demazure-type character formula for irreducible G-representations as a sum over lattice points (counted with sign according to a density function) of these twisted cubes. A twisted cube is untwisted when it is a "true" (i.e., closed, convex) polytope; in this case, Grossberg and Karshon's character formula becomes a purely positive formula with no multiplicities, i.e., each lattice point appears precisely once in the formula, with coefficient +1. One of our equivalent conditions for untwistedness is that a certain divisor on the special fiber of a toric degeneration of a Bott-Samelson variety, as constructed by Pasquier, is basepoint-free. We also show that the strict positivity of some of the defining constants for the twisted cube, together with convexity (of its support), is enough to guarantee untwistedness. Finally, in the special case when the twisted cube arises from the representation-theoretic data of $\lambda$ an integral weight and $\underline{w}$ a choice of word decomposition of a Weyl group element, we give two simple necessary conditions for untwistedness which is stated in terms of $\lambda$ and $\underline{w}$.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.4
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• pp.81-87
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• 1989

A cellular array multiplier for performing the multiplication of two elements in the finite field GF($2^m$) is presented in this paper. This multiplier is consisted of three operation part ; the multiplicative operation part, the modular operation part, and the primitive irreducible polynomial operation part. The multiplicative operation part and the modular operation part are composed by the basic cellular arrays designed AND gate and XOR gate. The primitive iirreducible operation part is constructed by XOR gates, D flip-flop circuits and a inverter. The multiplier presented here, is simple and regular for the wire routing and possesses the properties of concurrency and modularity. Also, it is expansible for the multiplication of two elements in the finite field increasing the degree m and suitable for VLSI implementation.

• Journal of the Korea Society of Computer and Information
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• v.20 no.2
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• pp.1-10
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• 2015

In this paper, we propose a new multiplication algorithm for primitive polynomial with all 1 of coefficient in case that m is odd and even on finite fields $GF(3^m)$, and design the multiplier with parallel input-output module structure using the presented multiplication algorithm. The proposed multiplier is designed $(m+1)^2$ same basic cells. Since the basic cells have no a latch circuit, the multiplicative circuit is very simple and is short the delay time $T_A+T_X$ per cell unit. The proposed multiplier is easy to extend the circuit with large m having regularity and modularity by cell array, and is suitable to the implementation of VLSI circuit.

• Journal of information and communication convergence engineering
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• v.9 no.4
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• pp.435-440
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• 2011

This paper propose the method of constructing the highly efficiency adder and multiplier systems over finite fields. The addition arithmetic operation over finite field is simple comparatively because that addition arithmetic operation is analyzed by each digit modP summation independently. But in case of multiplication arithmetic operation, we generate maximum k=2m-2 degree of ${\alpha}^k$ terms, therefore we decrease k into m-1 degree using irreducible primitive polynomial. We propose two method of control signal generation for the purpose of performing above decrease process. One method is the combinational logic expression and the other method is universal signal generation. The proposed method of constructing the highly adder/multiplier systems is as following. First of all, we obtain algorithms for addition and multiplication arithmetic operation based on the mathematical properties over finite fields, next we construct basic cell of A-cell and M-cell using T-gate and modP cyclic gate. Finally we construct adder module and multiplier module over finite fields after synthesizing ${\alpha}^k$ generation module and control signal CSt generation module with A-cell and M-cell. Next, we constructing the arithmetic operation unit over finite fields. Then, we propose the future research and prospects.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.43 no.5 s.311
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• pp.36-43
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• 2006

In this paper we present a new high-speed parallel multiplier for Performing the bit-parallel multiplication of two polynomials in the finite fields $GF(2^m)$. Prior to construct the multiplier circuits, we consist of the MOD operation part to generate the result of bit-parallel multiplication with one coefficient of a multiplicative polynomial after performing the parallel multiplication of a multiplicand polynomial with a irreducible polynomial. The basic cells of MOD operation part have two AND gates and two XOR gates. Using these MOD operation parts, we can obtain the multiplication results performing the bit-parallel multiplication of two polynomials. Extending this process, we show the design of the generalized circuits for degree m and a simple example of constructing the multiplier circuit over finite fields $GF(2^4)$. Also, the presented multiplier is simulated by PSpice. The multiplier presented in this paper use the MOD operation parts with the basic cells repeatedly, and is easy to extend the multiplication of two polynomials in the finite fields with very large degree m, and is suitable to VLSI. Also, since this circuit has a low propagation delay time generated by the gates during operating process because of not use the memory elements in the inside of multiplier circuit, this multiplier circuit realizes a high-speed operation.

• Journal of KIISE:Software and Applications
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• v.27 no.1
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• pp.50-61
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• 2000

Recently the stereo vision based on conics has received much attention by many authors. Conics have many features such as their matrix expression, efficient correspondence checking, abundance of conical shapes in real world. Extensions to higher algebraic curves met with limited success. Although irreducible algebraic curves are rather rare in the real world, lines and conics are abundant whose products provide good examples of higher algebraic curves. We consider plane algebraic curves of an arbitrary degree $n{\geq}2$ with a fully calibrated stereo system. We present closed form solutions to both correspondence and reconstruction problems. Let $f_1,\;f_2,\;{\pi}$ be image curves and plane and $VC_P(g)$ the cone with generator (plane) curve g and vertex P. Then the relation $VC_{O1}(f_1)\;=\;VC_{O1}(VC_{O2}(f_2)\;∩\;{\pi})$ gives polynomial equations in the coefficient $d_1,\;d_2,\;d_3$ of the plane ${\pi}$. After some manipulations, we get an extremely simple polynomial equation in a single variable whose unique real positive root plays the key role. It is then followed by evaluating $O(n^2)$ polynomials of a single variable at the root. It is in contrast to the past works which usually involve a simultaneous system of multivariate polynomial equations. We checked our algorithm using synthetic as well as real world images.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.3
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• pp.628-636
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• 2010

In this paper, we present a new type high speed parallel multiplier for performing the multiplication of two polynomials using standard basis in the finite fields GF($2^m$). Prior to construct the multiplier circuits, we design the basic cell of vector code generator(VCG) to perform the parallel multiplication of a multiplicand polynomial with a irreducible polynomial and design the partial product result cell(PPC) to generate the result of bit-parallel multiplication with one coefficient of a multiplicative polynomial with VCG circuits. The presented multiplier performs high speed parallel multiplication to connect PPC with VCG. The basic cell of VCG and PPC consists of one AND gate and one XOR gate respectively. Extending this process, we show the design of the generalized circuits for degree m and a simple example of constructing the multiplier circuit over finite fields GF($2^4$). Also, the presented multiplier is simulated by PSpice. The multiplier presented in this paper uses the VCGs and PPCS repeatedly, and is easy to extend the multiplication of two polynomials in the finite fields with very large degree m, and is suitable to VLSL.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.8
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• pp.35-45
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• 1999

In this paper, the addition and the multiplicative algorithm of two polynomials over finite field $GF(p^m)$ are presented. The 4-valued arithmetic processor of the serial input-parallel output modular structure on $GF(4^3)$ to be performed the presented algorithm is implemented by current mode CMOS. This 4-valued arithmetic processor using current mode CMOS is implemented one addition/multiplication selection circuit and three operation circuits; mod(4) multiplicative operation circuit, MOD operation circuit made by two mod(4) addition operation circuits, and primitive irreducible polynomial operation circuit to be performing same operation as mod(4) multiplicative operation circuit. These operation circuits are simulated under $2{\mu}m$ CMOS standard technology, $15{\mu}A$ unit current, and 3.3V VDD voltage using PSpice. The simulation results have shown the satisfying current characteristics. The presented 4-valued arithmetic processor using current mode CMOS is simple and regular for wire routing and possesses the property of modularity. Also, it is expansible for the addition and the multiplication of two polynomials on finite field increasing the degree m and suitable for VLSI implementation.