• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.07a
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• pp.185-186
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• 2005

Intrinsic gettering is usually used to improve wafer quality which is an important factor for reliable ULSI devices. The two-step annealing method was adopted in order to investigate interactions between oxygens and secondary defects during oxygen precipitation process in lightly and heavily boron doped silicon wafers with high energy $^{11}B^+$ ion implantation. Secondary defects were inspected nearby the projected range by high resolution transmission electron microscopy. Oxygen pileup was measured in the vicinity of the projected range by secondary ion mass spectrometry for heavily boron doped silicon wafers.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.8
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• pp.94-106
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• 1995

A three-dimensional(3D) Monte Carlo simulator for boron ion implantation into <100>single-crystal silicon considering the mask structure has been developed to predict the mask-dependent impurity doping profiles of the implanted boron at low energies into the reduced area according to the trend of a reduction in the size of semiconductor devices. All relevant important parameters during ion implantation have been taken into account in this simulator. These are incident energy, tilt and rotation of wafer, orientation of silicon wafer, presence of native silicon dioxide layer, dose, wafer temperature, ion beam divergence, masking thickness, and size and structure of open window in the mask. The one-dimensional(1D) results obtained by using the 3D simulator have been compared with the SIMS experiments to demonstrate its capabilities and confirem its reliability, and we obtained relatively accurate 1D doping profiles. Through these 3D simulations considering the hole structure and its size, we found the mask effects during boron ion implantation process.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.11 no.10
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• pp.796-803
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• 1998

Intrinsic and proximity gettering are popular processes to get higher cumulative production yield and usually adopt multi-step annealing and high energy ion implantation, respectively. In order to test the combined processed of these, high energy \ulcornerAs\ulcorner ion implantation and 2-step annealing process were adopted. After the ion implantation followed by 2-step annealing, the wafers were cleaved and etched with Wright etchant. The morphology of cross section on samples was inspected by FESEM. The concentration profile of As was measured by SRP. The location and type of secondary defects inspected by HRTEM were dependent on the 1st annealing temperatures. That is, a line of dislocation located at $1.5mutextrm{m}$ apart from the surface at $600^{\circ}C$ lst annealing was changed to some dislocation lines or loops nearby the surface at 100$0^{\circ}C$. The density of dislocation line was reduced but the size of the defects was enlarged as the temperature increased.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.35D no.12
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• pp.30-40
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• 1998

We have calculated ultra-low energy silicon-self ion implantations and silicon damages through classical molecular dynamics simulation using empirical potentials. We tested whether the recently developed Environment-Dependent Interatomic Potential(EDIP) was suitable for ultra low energy ion implantation simulation, and found that point defects formation energies were in good agreement with other theoretical calculations, but the calculated vacancy migration energy was overestimated. Most of the damages that are produced by collision cascades are concentrated into amorphous-like pockets. Also, We upgraded MDRANGE code for silicon ion implantation process simulation. We simulated ultra-low energy boron ion implantation, 200eV, 500eV, and 1000eV respectively, and calculated boron profiles with silicon substrate temperature and tilt angle. We investigated that below 1000eV, channeling effect must be considered.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.5
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• pp.375-381
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• 2001

As the device geometry continuously shrink down less than sub-quarter micrometer, DRAM makers are going to replace conventional tungsten-polycide bit-line with tungsten bit-line structure in order to reduce the chip size and use it as a local interconnection. In this paper we showed low resistance tungsten bit-line fabrication process with various RTP(Rapid Thermal Process) temperature and additional ion implantation. As a result we obtained that major parameters impact on tungsten bit-line process are RTP Anneal temperature and BF$_2$ ion implantation dopant. These tungsten bit-line process are promising to fabricate high density chip technology.

• Transactions on Electrical and Electronic Materials
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• v.13 no.4
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• pp.188-191
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• 2012

This paper introduces a new method regarding deuterium incorporation in the gate dielectric including deuterium implantation and post-annealing at the back-end-of-the process line. The control device and the deuterium furnace-annealed device were also prepared for comparison with the implanted device. It was observed that deuterium implantation at a light dose of $1{\times}10^{12}-1{\times}10^{14}/cm^2$ at 30 keV reduced hot-carrier injection (HCI) degradation and negative bias temperature instability (NBTI) within our device structure due to the reduction in oxide charge and interface trap. Deuterium implantation provides a possible solution to enhance the bulk and interface reliabilities of the gate oxide under the electrical stress.

• Journal of the Korean Vacuum Society
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• v.13 no.1
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• pp.1-8
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• 2004

The SOI wafer fabrication technique has been developed by using ion-cut process, based on proton implantation and wafer bonding techniques. It has been shown by TRIM simulation that 65 keV proton implantation is required for the standard SOI wafer (200 nm SOI, 400 nm BOX) fabrication. In order to investigate the optimum proton dose and primary annealing condition for wafer splitting, the surface morphologic change has been observed such as blistering and flaking. As a result, effective dose is found to be in the 6∼$9\times10^{16}$ $H^{+}/\textrm{cm}^2$ range, and the annealing at $550^{\circ}C$ for 30 minutes is expected to be optimum for wafer splitting. The depth distribution of implanted hydrogen has been experimentally confirmed by ERD and SIMS measurements. The microstructure evolution in the damaged layer was also studied by X-TEM analysis.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.07a
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• pp.115-117
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• 2005

In this paper, we formed the shallow junction by preamorphization and low energy ion implantation. And a simulator is designed for predicting the annealing process results. Especially, if considered the applicable to single step annealing process(RTA, FA) and dual step annealing process(RTA+FA, FA+RTA). In this simulation, the ion implantation model and the boron diffusion model are used. The Monte Carlo model is used for the ion implantation. Boron diffusion model is based on pair diffusion at nonequilibrium condition. And we considered that the BI-pairs lead the diffusion and the boron activation and clustering reaction. Using the boundary condition and initial condition, the diffusion equation is solved successfully. The simulator is made ofC language and reappear the experimental data successfully.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.04b
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• pp.30-33
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• 2004

Shallow p+-n junctions were formed by low-energy ion implantation and dual-step annealing processes The dopant implantation was performed into the crystalline substrates using $BF_2$ ions. The annealing was performed with a rapid thermal processor and a furnace. FA+RTA annealing sequence exhibited better junction characteristics than RTA+FA thermal cycle from the viewpoint of junction depth. A new simulator is designed to model boron diffusion in silicon, which is especially useful for analyzing the annealing process subsequent to ion implantation. The model which is used in this simulator takes into account nonequilibrium diffusion, reactions of point defects, and defect-dopant pairs considering their charge states, and the dopant inactivation by introducing a boron clustering reaction. Using a resonable parameter values, the simulator covers not only the equilibrium diffusion conditions but also the nonequilibrium post-implantation diffusion. Using initial conditions and boundary conditions, coupled diffusion equation is solved successfully. The simulator reproduced experimental data successfully.

• Journal of IKEEE
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• v.26 no.3
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• pp.333-340
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• 2022

Process and device simulations were performed to determine the optimal ion implantation conditions to prevent double snapback of high voltage operating DDDNMOS (double diffused drain N-type MOSFET) device for ESD protection. By examining the effects of HP-Well, N^- drift and N⁺ drain ion implantation on the double snapback and avalanche breakdown voltages, it was possible to prevent double snapback and improve the electrostatic protection performance. If the ion implantation concentration of the N^- drift region rather than the HP-Well region is optimally designed, it prevents the transition from the primary on-state to the secondary on-state, so that relatively good ESD protection performance can be obtained. Since the concentration of the N^- drift region affects the leakage current and the avalanche breakdown voltage, in the case of a process technology with an operating voltage greater than 30V, a new structure such as DPS or colligation of optimal process conditions can be applied. In this case, improved ESD protection performance can be realized.