Journal of IKEEE (전기전자학회논문지)

Institute of Korean Electrical and Electronics Engineers (한국전기전자학회)
권호 표지
DOI QR코드

DOI QR Code

Determination of optimal ion implantation conditions to prevent double snapback of high voltage operating DDDNMOS device for ESD protection

고전압 정전기 보호용 DDDNMOS 소자의 더블 스냅백 방지를 위한 최적의 이온주입 조건 결정

  • Received : 2022.07.26
  • Accepted : 2022.09.19
  • Published : 2022.09.30
Download PDF
⟨ Previous Next ⟩

Abstract

Process and device simulations were performed to determine the optimal ion implantation conditions to prevent double snapback of high voltage operating DDDNMOS (double diffused drain N-type MOSFET) device for ESD protection. By examining the effects of HP-Well, N- drift and N+ drain ion implantation on the double snapback and avalanche breakdown voltages, it was possible to prevent double snapback and improve the electrostatic protection performance. If the ion implantation concentration of the N- drift region rather than the HP-Well region is optimally designed, it prevents the transition from the primary on-state to the secondary on-state, so that relatively good ESD protection performance can be obtained. Since the concentration of the N- drift region affects the leakage current and the avalanche breakdown voltage, in the case of a process technology with an operating voltage greater than 30V, a new structure such as DPS or colligation of optimal process conditions can be applied. In this case, improved ESD protection performance can be realized.

고전압용 정전기 보호소자인 DDDNMOS(double diffused drain N-type MOSFET) 소자의 더블 스냅백 방지를 위한 최적의 이온주입 조건을 결정하기 위해 공정 및 소자 시뮬레이션이 수행되었다. HP-Well, N- 드리프트 및 N+ 드레인 이온주입량의 변화가 더블 스냅백 및 애발란치 브레이크다운 전압에 미치는 영향을 고찰함으로써 더블 스냅백을 방지하여 정전기 보호 성능 개선할 수 있었다. HP-Well 영역보다는 N- 드리프트 영역의 이온주입 농도를 최적으로 설계할 경우, 1차 on 상태에서 2차 on 상태로 전이하는 것을 막아주므로 비교적 양호한 정전기 보호 성능을 얻을 수 있었다. 또한 드리프트 이온주입 농도는 누설전류 및 애발란치 브레이크다운 전압에도 영향을 미치므로 동작전압이 30V보다 큰 공정기술에서는 DPS와 같은 새로운 구조를 적용하거나, 대안으로 여러 공정 변수들을 종합(colligation)하여 적용할 경우 향상된 정전기 보호 성능을 실현할 수 있을 것이다.

Keywords

Acknowledgement

This work was supported by the Seahn university research fund in 2022.

References

  1. M. P. J. Mergens, W. Wilkening, S. Mettler, H. Wolf, A. Stricker and W. Fichtner, "Analysis of lateral DMOS power devices under ESD stress conditions," IEEE Trans. Electron Devices, Vol.47, pp.2128-2137, 2000. DOI: 10.1109/16.877175
  2. K. Kawamoto, S. Takahashi, S. Fujino and I. Shirakawa, "A no-snapback LDMOSFET with automotive ESD endurance," IEEE Trans. Electron Devices, Vol.49, pp.2047-2053, 2002. DOI: 10.1109/TED.2002.804734
  3. G. Bosselli, S. Meeuwsen, T. Mouthaan and F. Kuper, "Investigations on double diffused MOS (DMOS) transistors under ESD zap conditions," in Proc. EOS/ESD Symp., pp.11-18, 1999. DOI: 10.1109/EOSESD.1999.818984
  4. M. D. Ker and K. H. Lin, Double snapback characteristics in high-voltage nMOSFETs and the impact on-chip ESD protection, IEEE Electron Dev. Lett., Vol.25, No.9, pp.640-642, 2004. DOI:10.1109/LED.2004.833372
  5. J. W. Yang and, Y. J. Seo, "Improvements of Extended Drain NMOS (EDNMOS) Device for Electrostatic Discharge (ESD) Protection of High Voltage Operating LDI Chip," Journal of Satellite, Information and Communications, Vol.7, No.2, pp.18-24, 2012.
  6. Y. J. Seo and K. H. Kim, "Characteristics of an extended drain N-type MOS device for electrostatic discharge protection of a LCD driver chip operating at high voltage," J. Korean Phys. Soc., Vol.50, No.3, pp.897-901, 2007. DOI: 10.3938/jkps.50.897
  7. Y. J. Seo and K. H. Kim, "Effects of background doping concentration on electrostatic discharge protection of high voltage operating extended drain N-type MOS device," Microelectronic Engineering, Vol.84, No.1, pp.161-164, 2007. DOI: 10.1016/j.mee.2006.09.030
  8. J. E. Barth, K. Verhaege, L. G. Henry, and J. Richner, "TLP calibration, correlation, standards, and new techniques," IEEE Trans. Electron. Packaging Manufact., Vol.24, No.2, pp.99-108, 2001. DOI:10.1109/6104.930960
  9. Y. J. Seo and J. W. Yang, "Improvements of ESD Protection Performance of High Voltage Operating EDNMOS Device with DPS (Double Polarity Source) Structure," Journal of Satellite, Information and Communications, Vol.9, No.2, pp.12-17, 2014.