• The Journal of the Acoustical Society of Korea
• /
• v.19 no.3
• /
• pp.26-34
• /
• 2000

In this paper, we propose a 4kbps speech coder that combines the harmonic vector excitation coding with time-separated transition coding. The harmonic vector excitation coding uses the harmonic excitation coding in the voiced frame and uses the vector excitation coding with the structure of analysis-by-synthesis in the unvoiced frame, respectively. But two mode coding method is not effective for transition frame mixed in voiced and unvoiced signal and a new method beyond using unvoiced/voiced mode coding is needed. Thus, we designed a time-separated transition coding method for transition frame in which a voiced/unvoiced decision algorithm separates unvoiced and voiced duration in a frame, and harmonic-harmonic excitation coding and vector-harmonic excitation coding method is selectively used depending on the previous frame U/V decision. In the decoder, the voiced excitation signals are generated efficiently through the inverse FFT of harmonic magnitudes and the unvoiced excitation signals are made by the inverse vector quantization. The reconstructed speech signal are synthesized by the Overlap/Add method.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
• /
• v.1 no.3
• /
• pp.97-103
• /
• 2008

In this paper, $256{\times}256$ input image is classified into a validity block and an edge block of $8{\times}8$ block for image compression. DCT(Discrete Cosine Transform) is executed only for the DC coefficient that is validity coefficients for a validity block. Predict the position where a quantization coefficient becomes 0 for an edge block, I propose new algorithm to execute DCT in the reduced region. Not only this algorithm that I proposed reduces computational complexity of FDCT(Forward DCT) and IDCT(Inverse DCT) and decreases encoding time and decoding time. I let compressibility increase by accomplishing other stability verticality zigzag scan by the block size that was classified for each block at the time of huffman encoding each. In addition, the algorithm that I suggested reduces Run-Length by accomplishing the level verticality zigzag scan that is good for a classified block characteristic and, I offer the compressibility that improved thereby.

• KSII Transactions on Internet and Information Systems (TIIS)
• /
• v.11 no.5
• /
• pp.2701-2722
• /
• 2017

Key generation is essential for protecting wireless networks. Based on wireless channel reciprocity, transceivers can generate shared secret keys by measuring their communicating channels. However, due to non-simultaneous measurements, asymmetric noises and other interferences, channel measurements collected by different transceivers are highly correlated but not identical and thus might have some discrepancies. Further, these discrepancies might lead to mismatches of bit sequences after quantization. The referred mismatches significantly affect the efficiency of key generation. In this paper, an efficient key generation scheme leveraging wireless channel reciprocity is proposed. To reduce the bit mismatch rate and enhance the efficiency of key generation, the involved transceivers separately apply discrete cosine transform (DCT) and inverse discrete cosine transform (IDCT) to pre-process their measurements. Then, the outputs of IDCT are quantified and encoded to establish the bit sequence. With the implementations of information reconciliation and privacy amplification, the shared secret key can be generated. Several experiments in real environments are conducted to evaluate the proposed scheme. During each experiment, the shared key is established from the received signal strength (RSS) of heterogeneous devices. The results of experiments demonstrate that the proposed scheme can efficiently generate shared secret keys between transceivers.

• Proceedings of the IEEK Conference
• /
• 2006.06a
• /
• pp.257-258
• /
• 2006

In this paper, we address several issues in the real time implementation of MPEG-1 Layer II decoder on a fixed-point digital signal processor (DSP), especially TMS320C6416. There is a trade-off between processing speed and the size of program/data memory for the optimal implementation. In a view of the speed optimization, we first convert the floating point operations into fixed point ones with little degradation in audio quality, and then the look-up tables used for the inverse quantization of the audio codec are forced to be located into the internal memory of the DSP. And then, window functions and filter coefficients in the decoder are precalculated and stored as constant, which makes the decoder faster even larger memory size is required. It is shown from the real-time experiments that the fixed-point implementation enables us to make the decoder with a sampling rate of 48 kHz operate with 3 times faster than real-time on TMS320C6416 at a clock rate of 600 MHz.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2018.10a
• /
• pp.180-181
• /
• 2018

JPEG is a most widely used standard image compression technology. This research introduces the JPEG image compression algorithm and describes each step in the compression and decompression. Image compression is the application of data compression on digital images. The DCT (discrete cosine transform) is a technique for converting a time domain to a frequency domain. First, the image is divided into 8 by 8 pixel blocks. Second, working from top to bottom left to right, the DCT is applied to each block. Third, each block is compressed through quantization. Fourth, the array of compressed blocks that make up the image is stored in a greatly reduced amount of space. Finally if desired, the image is reconstructed through decompression, a process using IDCT (inverse discrete cosine transform).

• Journal of the Institute of Convergence Signal Processing
• /
• v.15 no.1
• /
• pp.1-8
• /
• 2014

Digital watermarking techniques are attracting attention as a proper solution to protect copyright for multimedia data. This paper proposes a new audio watermarking method based on Discrete Cosine Transformation (DCT) and Discrete Wavelet Transformation (DWT) for copyright protection. In our proposed watermarking method, the original audio is transformed into DCT domain and divided into two parts. Synchronization code is applied on the signal in first part and 2 levels DWT domain is applied on the signal in second part. The absolute value of DWT coefficient is divided into arbitrary number of segments and calculates the energy of each segment and middle peak. Watermarks are then embedded into each middle peak. Watermarks are extracted by performing the inverse operation of watermark embedding process. Experimental results show that the hidden watermark data is robust to re-sampling, low-pass filtering, re-quantization, MP3 compression, cropping, echo addition, delay, and pitch shifting, amplitude change. Performance analysis of the proposed scheme shows low error probability rates.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2015.10a
• /
• pp.416-419
• /
• 2015

In this paper, we propose an effective design of transform hardware for real-time HEVC(High Efficiency Video Coding) encoder. HEVC encoder determines the transform mode($4{\times}4$, $8{\times}8$, $16{\times}16$, $32{\times}32$) by comparing RDCost. RDCost require a significant amount of computation and time because it is determined by bit-rate and distortion which is computated via transform, quantization, dequantization, and inverse transform. This paper therefore proposes a new method for transform mode determination using sum of transform coefficient. Also, proposed hardware architecture is implemented with multiplexer, recursive adder/subtracter, and shifter only to derive reduction of the computation. Proposed method for transform mode determination results in an increase of 0.096 in BD-PSNR, 0.057 in BD-Bitrate, and decrease of 9.3% in encoding time by comparing HM 10.0. The hardware which is proposed is implemented by 256K logic gates in TSMC 130nm process. Its maximum operation frequency is 200MHz. At 140MHz, the proposed hardware can support 4K Ultra HD video encoding at 60fps in real time.

• Journal of the Korea Society of Computer and Information
• /
• v.15 no.2
• /
• pp.109-117
• /
• 2010

Digital watermarking has drawn extensive attention for protecting digital contents from unauthorized copying. This paper proposes a new watermarking scheme in frequency domain for copyright protection of digital audio. In our proposed watermarking system, the original audio is segmented into non-overlapping frames. Watermarks are then embedded into the selected prominent peaks in the magnitude spectrum of each frame. Watermarks are extracted by performing the inverse operation of watermark embedding process. Simulation results indicate that the proposed scheme is robust against various kinds of attacks such as noise addition, cropping, resampling, re-quantization, MP3 compression, and low pass filtering. Our proposed watermarking system outperforms Cox's method in terms of imperceptibility, while keeping comparable robustness with the Cox's method. Our proposed system achieves SNR (signal-to-noise ratio) values ranging from 20 dB to 28 dB. This is in contrast to Cox's method which achieves SNR values ranging from only 14 dB to 23 dB.

• Journal of the Institute of Electronics Engineers of Korea TC
• /
• v.47 no.10
• /
• pp.36-42
• /
• 2010

FFT(Fast Fourier Transform) processor is one of the key components in the implementation of OFDM systems for many wireless standards such as IEEE 802.22. To improve the performances of FFT processors, various studies have been carried out to reduce the complexities of multipliers, memory interface, control schemes and so on. While the number of FFT stages increases logarithmically $log_2N$) as the FFT point-size (N) increases, the number of required registers (or, memories) increases linearly. In large point-size FFT designs, the registers occupy more than 70% of the chip area. In this paper, to reduce the memory size of IFFT for OFDM transmitters, we propose a new IFFT design method based on a combined mapping of modulated data, pilot and null signals. The proposed method focuses on reducing the sizes of the registers in the first two stages of the IFFT architectures since the first two stages require 75% of the total registers. By simulations of 2048-point IFFT design for cognitive radio systems, it is shown that the proposed IFFT design method achieves more than 38.5% area reduction compared with previous IFFT designs.