• The Transactions of the Korean Institute of Electrical Engineers A
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• v.50 no.4
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• pp.157-165
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• 2001

The two criteria to identify the disturbances of the power transformer has been reported in this paper. They have been derived through EMTP simulations of internal faults, inrush and overexcitation for the model of 154/22.9[kV], 40[MVA], Y-Y three-phase power transformer. We propose the crisp algorithm which uses two criteria. A series of test results clearly indicate that the method can identify not only an internal fault but also the other transients. The average of relay operation times is about 7.2[ms]. The proposed algorithm immunes to the transient state.

• Proceedings of the KIEE Conference
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• 2003.11a
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• pp.210-212
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• 2003

Conventional PDC relaying with 2nd harmonic restraint makes some doubt in reliability. It can contain second harmonic component to a large extent even during internal fault, and shows a tendency of relative reduction because of the advancement of transformer's core material. It is, therefore, necessary to develop a new algorithm as well as a new technique for the effective and accurate discrimination. This paper deals with advanced algorithm, fuzzy logic based relaying by using flux differential, and a new fault detection criterion logic scheme by using wavelet transform. To comparative analysis of proposed techniques, the paper constructs power system model including power transformer, utilizing the EMTP, and collects data through simulation of various internal faults and magnetizing inrush.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.17 no.5
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• pp.43-50
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• 2003

This presents a fault detecting method for a power transformer based upon a neural network. To maintain a normal relay operating conditions, external winding faults of a power transformer and magnetic inrush have been tested under consideration of the EMTP/ATP software and internal faults of power transformer have been tested by the EMTP/BCTRAN software. The neural network has been evaluated by the proposed fault. Input variables of the neural network for the proposed model can be obtained from fundamental currents, restraining and operating currents. This algorithm uses back-propagation and the ratio of a restraining current and an operating current as relay input parameters. The ratio may enhance the fault detection since the restraining currents increase rapidly at external faults. The proposed detecting method has been applied to the practical relay systems for transformer protection. As a result, the proposed detecting method based on the neural network has been shown to have better characteristics.

• Journal of the Korean Institute of Telematics and Electronics
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• v.11 no.4
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• pp.17-22
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• 1974

In this paper, the problem of finding tests to detect faults in combinational logic circuits is considered. At first, the method of fault detection in fan-out-free irredundant circuits is derived, and the result is extended to the fan-out redundant circuits. A fan-out circuit is decomposed into a set of fan-out-free subcircuits by cutting the lines at the internal fan-out points, and the minimal detecting test. sets for each subcircuit are found separately. And then, the compatible tests from each test set are combined maximally into composite tests to generate primary input binary vectors. By this procedure. the minimal complete test sets for reconvergent fan-out circuits are easily found and the detectable and undetectable faults are also classified clearly.

• Proceedings of the Korean Institute of IIIuminating and Electrical Installation Engineers Conference
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• 2007.11a
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• pp.195-197
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• 2007

This paper presents experimental results on the safety of persons due to a ground fault in 22.9 kV-Y distribution system In order to evaluate the touch voltages due to internal ground faults in a step down transformer based on the newly prescribed KS C IEC 60364 standard series, the verification tests in a 22.9 kV multi-grounded neutral system were carried out From the experimental results, it was found that there will be significant potential rise jeopardizing LV equipment insulation in case of separate grounding between HV and LV system and the effective measures against hazardous touch voltages due to a IN side ground fault in the common grounding system between HV and LV system are proposed. As a consequence, it was found that the equipotential bonding is an important prerequisite for the effectiveness of the protective measures for the safety of persons in the common ground system between 22.9 kV-Y and low-voltage grounding system.

• Journal of Electrical Engineering and Technology
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• v.10 no.3
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• pp.740-754
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• 2015

This paper focuses on the reverse blocking busbar protection scheme with aim to improve the speed of its operation and at the same time to increase operational reliability, flexibility and stability of the protection during external and internal faults by implementation of the extended functionality provided by the IEC61850 standard-based protective Intelligent Electronic Devices (IEDs). The practical implementation of the scheme by the use of IEC 61850 standard communication protocol is investigated. The proposed scheme is designed for a radial type of a distribution network and is modeled and simulated in the DigSILENT software environment for various faults on the busbar and its outgoing feeders. A laboratory test bench is built using three ABB IEDs 670 series that are compliant with the IEC 61850 standard, CMC 356 Omicron test injection device, PC, MOXA switch, and a DC power supplier. Two types of the reverse blocking signals between the IEDs in the test bench are considered: hard wired and Ethernet communication by using IEC 61850 standard GOOSE messages. Comparative experimental study of the operational trip response speeds of the two implementations for various traffic conditions of the communication network shows that the performance of the protection scheme for the case of Ethernet IEC 61850 standard-based communication is better.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.45 no.4
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• pp.490-500
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• 1996

The conventional method to deal with current transformer (CT) Saturation is over dimensioning of the core so that CTs can carry up to 20 times the rated current without exceeding 10% ratio correction. However, this not only reduces the sensitivity of relays as some errors may still be present in the secondary current when a severe fault occurs, but also increases the CT size. This paper presents an algorithm for compensating the distorted secondary current of iron-cored CTs under CT saturation using the magnetization (flux-current : .lambda.-i) curve and its performance is examined for fault currents encountered on a typical 345[kV] Korean transmission system, under a variety of different system and fault conditions. In addition, the results of hardware implementation of the algorithm using a TMS320C10 digital signal processor are also presented. The proposed algorithm can improve the sensitivity of relays to low level internal faults, maximize the stability of relays for external faults, and reduce the required CT core cross-section significantly. (author). refs., figs.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.55 no.1
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• pp.6-12
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• 2006

A popular method used by primary protection for power transformer is current ratio differential relaying (RDR) with 2nd harmonic restraints. In modern power transformer due to the use of low-loss amorphous material, the 2nd harmonic component during inrush is significantly reduced. The higher the capacitance of the high voltage status and underground distribution, the more the differential current includes the 2nd harmonic component during internal fault. Thus the conventional method may not operate properly. This paper proposes an advanced relaying algorithm and the prototype IED hardware design and it's real-time experimental results. To evaluate performance of the proposed algorithm, the study is well constructed power system model including power transformer utilizing the EMTP software and the testing is made through simulation of various cases. The proposed relaying that is well constructed using DSP chip and microprocessor etc. has been developed and the prototype IED has been verified through on-line testing. The results show that an advanced relaying based prototype IED never mis-operated and correctly identified all the faults and that inrushes that are applied.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.53 no.2
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• pp.43-50
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• 2004

Percentage differential characteristic relaying(PDR) has been recognized as the principal basis for power transformer protection. Second harmonic restraint PDR has been widely used for magnetizing inrush in practice. Nowadays, relaying signals can contain 2nd harmonic component to a large extent even in a normal state, and 2nd harmonic ratio indicates a tendency of relative reduction because of the advancement of material. Further, as the power system voltage becomes higher and more underground cables are used, larger 2nd harmonic component in the differential current under internal fault is observed. And then, conventional 2nd harmonic restraint PDR exposes some doubt in reliability. It is, therefore, necessary to develop a new algorithm for performance improvement of conventional protective relaying. This paper proposes an advanced protective relaying algorithm by using voltage-current trend and flux-differential current slope characteristic. To evaluate the performance of the proposed algorithm, we have made comparative studies of PDR, fuzzy relaying and DWT relaying. The paper is constructed power system model including power transformer, utilizing the WatATP, and data collection is made through simulation of various internal faults and inrush. As the results of test, the new proposed algorithm was proven to be faster and more reliable.

• Journal of the Korea Society of Computer and Information
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• v.6 no.1
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• pp.7-13
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• 2001

As the density of VLSI increases, the conventional logic testing is not sufficient to completely detect the new faults generated in design and fabrication processing. Recently. IDDQ testing becomes very attractive since it can overcome the limitations of logic testing. This paper presents a new BIC for the internal current test in CMOS logic circuit. Our circuit is composed of Magnetoresistive current sensor, level shifter, comparator, reference voltage circuit and a circuit be IDDQ tested as a kind of self-testing fashion by using the proposed BIC.