• Title/Summary/Keyword: interleaving

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Enhancing the Image Transmission over Wireless Networks through a Novel Interleaver

  • El-Bendary, Mohsen A.M.;Abou-El-Azm, A.E.;El-Fishawy, N.A.;Shawki, F.;El-Tokhy, M.;Abd El-Samie, F.E.;Kazemian, H.B.
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • v.5 no.9
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    • pp.1528-1543
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    • 2011
  • With increasing the using of wireless technologies in essential fields such as the medical application, this paper proposes different scenarios for the transmission of images over wireless networks. The paper uses the IEEE ZigBee 802.15.4 for applying the proposed schemes. It is a Wireless Personal Area Network (WPAN). This paper presents a novel chaotic interleaving scheme against error bursts. Also, the paper studies the proposed interleaver with the convolutional code with different constraint lengths (K). A comparison study between the standard scheme and proposed schemes for image transmission over a correlated fading channel is presented. The simulation results show the superiority of the proposed chaotic interleaving scheme over the traditional schemes. Also, the chaotic interleaver packet-by-packet basis gives a high quality image with (K=3) and reduces the need for the complex encoder with K=7.

3-Level Boost Converter Having Lower Inductor for Interleaving Operation (인터리빙 동작을 위한 하단 인덕터를 갖는 3-Level Boost Converter)

  • Lee, Kang-Mun;Baek, Seung-Woo;Kim, Hag-Wone;Cho, Kwan-Yuhl;Kang, Jeong-Won
    • The Transactions of the Korean Institute of Power Electronics
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    • v.26 no.2
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    • pp.96-105
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    • 2021
  • Large-scale power converters consist of series or parallel module combinations. In these modular converter systems, the interleaving technique can be applied to improve capacitor reliability by reducing the ripple of the I/O current in which each module operates as a phase difference. However, when applying the interleaving technique for conventional three-level boost converters, the short-circuit period of the converter can be an obstacle. Such problem is caused by the absence of a low-level inductor of the conventional three-level boost converter. To solve this problem, a three-level boost converter with a low-level inductor is proposed and analyzed to enable interleaved operation. In the proposed circuit, the current ripple of the output capacitor depends on the neutral point connections between the modules. In this study, the ripple current is analyzed by the neutral point connections of the three-level boost converter that has a low-level inductor, and the effectiveness of the proposed circuit is proven by simulation and experiment.

Dynamic Allocation Algorithm for enhancement of transmission performance on a radio encryption system (무선암호시스템에서 전송성능 개선을 위한 동적할당 알고리듬)

  • 홍진근;윤장홍;장병화;황찬식
    • Journal of the Korea Institute of Information Security & Cryptology
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    • v.11 no.1
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    • pp.3-12
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    • 2001
  • In this paper, a synchronized stream encryption system for secure link layer communication in a radio channel is designed. Interleaving scheme which is used to enhance the transmission performance over a fading channel is applied to the encrypted information. A designed synchronous scream cipher system consists of a keystream generator, a synchronization pattern generator and a session key generator. The structure of a synchronous stream cipher system with periodic synchronization is composed of the encrypted information which consists of a synchronization pattern, an error correcting coded session key, an encrypted data in a period of synchronization. In this paper, interleaving scheme using dynamic allocation a1gorithm(DAA) is applied the encrypted information. The BER of the DAA has been slightly higher than that of the SAA(static allocation algorithm).

Architecture Design of Turbo Codec using on-the-fly interleaving (On-the-fly 인터리빙 방식의 터보코덱의 아키텍쳐 설계)

  • Lee, Sung-Gyu;Song, Na-Gun;Kay, Yong-Chul
    • The KIPS Transactions:PartC
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    • v.10C no.2
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    • pp.233-240
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    • 2003
  • In this paper, an improved architecture of turbo codec for IMT-2000 is proposed. The encoder consists of an interleaver using an on-the-fly type address generator and a modified shift register instead of an external RAM, and the decoder uses a decreased number of RAM. The proposed architecture is simulated with C/VHDL languages, where BER (bit-error-rate) performances are generally in agreement with previous data by varying interaction numbers, interleaver block sizes and code rates.

Polarization-Independent Multiwavelength-Switchable Filter Based on Polarization Beam Splitter and Fiber Coupler

  • Lee, Yong-Wook
    • Journal of Electrical Engineering and Technology
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    • v.4 no.3
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    • pp.405-409
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    • 2009
  • A polarization-independent multiwavelength-switchable fiber filter is proposed based on a polarization beam splitter and fiber coupler, which can function as a polarization-independent transmission or reflection-type interleaving filter. The proposed filter consists of a polarization beam splitter and a Sagnac birefringence loop composed of a 50:50 coupler, high birefringent fibers, and two quarter-wave plates. In the proposed filter, a transmission-type interleaver with a channel isolation > 18 dB or a reflection-type one with a channel isolation of ${\sim}3$ dB, whose channel spacing and switching displacement were 0.8 and 0.4 nm in common, respectively, could be obtained. A channel interleaving operation could be performed by the proper control of waveplates within the Sagnac birefringence loop.

Efficient Exponentiation in Extensions of Finite Fields without Fast Frobenius Mappings

  • Nogami, Yasuyuki;Kato, Hidehiro;Nekado, Kenta;Morikawa, Yoshitaka
    • ETRI Journal
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    • v.30 no.6
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    • pp.818-825
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    • 2008
  • This paper proposes an exponentiation method with Frobenius mappings. The main target is an exponentiation in an extension field. This idea can be applied for scalar multiplication of a rational point of an elliptic curve defined over an extension field. The proposed method is closely related to so-called interleaving exponentiation. Unlike interleaving exponentiation methods, it can carry out several exponentiations of the same base at once. This happens in some pairing-based applications. The efficiency of using Frobenius mappings for exponentiation in an extension field was well demonstrated by Avanzi and Mihailescu. Their exponentiation method efficiently decreases the number of multiplications by inversely using many Frobenius mappings. Compared to their method, although the number of multiplications needed for the proposed method increases about 20%, the number of Frobenius mappings becomes small. The proposed method is efficient for cases in which Frobenius mapping cannot be carried out quickly.

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An Autonomic -Interleaving Registry Overlay Network for Efficient Ubiquities Web Services Discovery Service

  • Ragab, Khaled
    • Journal of Information Processing Systems
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    • v.4 no.2
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    • pp.53-60
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    • 2008
  • The Web Services infrastructure is a distributed computing environment for service-sharing. Mechanisms for Web services Discovery proposed so far have assumed a centralized and peer-to-peer (P2P) registry. A discovery service with centralized architecture, such as UDDI, restricts the scalability of this environment, induces performance bottleneck and may result in single points of failure. A discovery service with P2P architecture enables a scalable and an efficient ubiquities web service discovery service that needs to be run in self-organized fashions. In this paper, we propose an autonomic -interleaving Registry Overlay Network (RgON) that enables web-services' providers/consumers to publish/discover services' advertisements, WSDL documents. The RgON, doubtless empowers consumers to discover web services associated with these advertisements within constant D logical hops over constant K physical hops with reasonable storage and bandwidth utilization as shown through simulation.

A Novel Paralleling Method of Converters for Reduction of Hippie in Output Voltage (컨버터의 출력전압 리플 저감을 위한 새로운 병렬운전 방법에 대한 연구)

  • Park, Sung-Woo;Park, Hee-Sung;Jang, Jin-Beak;Jang, Sung-Soo;Kim, Jong-Duck
    • Proceedings of the Korean Institute of IIIuminating and Electrical Installation Engineers Conference
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    • 2004.11a
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    • pp.237-240
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    • 2004
  • For the paralleled operation of DC/DC converters, the current sharing between each modules is the most important for the reliability of the power system. Interleaving method is commonly used with many paralleling schemes for the reduction of the ripple in the output voltage of paralleled converters and there are many commercial IC for interleaving application appliable. But for all of them, it is impossible to detect the number of module in operating and then change the phase of them automatically. In this paper, a novel paralleling method is proposed for the converter parallel operation, which detects the number of modules in active and sets the phases of PWM signals applied to each modules autonomously. This can greatly improve the output voltage ripple and reliability of the system. The expandibility of modular number can be done very easily by just adding several parts.

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Analysis of Shrinking Generator Using Phase Shifts (위상이동차를 이용한 수축 생성기의 분석)

  • Hwang, Yoon-Hee;Cho, Sung-Jin;Choi, Un-Sook
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.14 no.11
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    • pp.2507-2513
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    • 2010
  • In this paper, we show that the shrinking generator with two LFSR whose characteristic polynomials are primitive is an interleaving generator and analyze phase shifts in shrunken sequence. Also for a given intercepted sequence of shrunken sequence, we propose. the method of reconstructing some deterministic bits of the shrunken sequence using phase shifts.

New Configuration of 36-pulse Voltage Source Converter Using Pulse-Interleaving Auxiliary Circuit (펄스다중화 보조회로를 이용한 새로운 구조의 36-펄스 전압원 컨버터)

  • Jon Young-Soo;Baek Seung-Taek;Han Byung-Moon
    • The Transactions of the Korean Institute of Electrical Engineers B
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    • v.54 no.5
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    • pp.238-244
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    • 2005
  • This paper proposes a new configuration of 36-pulse voltage source converter which consists of two 6-pulse bridges and a pulse-interleaving auxiliary circuit. The system topology of proposed converter was derived to increase the pulse number of converter output voltage without increasing the number of 6-pulse bridges. The gate pulse generation was analyzed using the theoretical approach of multi-pulse switching converter, The operational feasibility of proposed system was verified by computer simulations with PSCAD/EMTDC software and experimental works with 2kVA hardware prototype. The proposed converter can be widely used for the uninterruptible power supply, the power quality compensator, and the distributed power generation, such as solar and fuel cell power system.