• Proceedings of the IEEK Conference
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• 2003.11c
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• pp.200-203
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• 2003

By minimizing the burst error of data and correcting the error, we can define the convolution coding and interleaving in IEEE 802.11a wireless tan system. Two step block interleaver was decided by coded bits per OFDM symbol and due to this it comes to the delay time in IEEE 802.11a. This is the point of the question which we must consider. We try to decrease the delay time by all 48-clock from interleavings, and we have proposed a way carried out the interleaving outputs per symbol. So in comparison with the existing interleaver, we can decrease the delay time in reading and writing data, as well as reduce the delay time of bit re-ordering per symbol. Also this scheme is apply in all x-QAM cases.

• Journal of Communications and Networks
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• v.15 no.6
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• pp.581-588
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• 2013

Based on an interleaving technique and quadriphase periodic complementary sequence (CS) mates, this paper presents a method for constructing a family of 16-quadrature amplitude modulation (QAM) periodic CS mates. The resulting mates arise from the conversion of quadriphase periodic CS mates, and the period of the former is twice as long as that of the latter. In addition, based on the existing binary periodic CS mates, a table on the existence of the proposed 16-QAM periodic CS mates is given. Furthermore, the proposed method can also transform a mutually orthogonal (MO) quadriphase CS set into an MO 16-QAM CS set. Finally, three examples are given to demonstrate the validity of the proposed method.

• 한국정보통신설비학회:학술대회논문집
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• 2005.08a
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• pp.427-430
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• 2005

A multi-code biorthogonal code keying (MBCK) system consists of multiple waveform coding blocks, and the sum of output codewords is transmitted. Drawback of MBCK is that it requires amplifier with high linearity because its output symbol is multi-level. MBCK with constant amplitude precoding block (CA-MBCK) has been proposed, which guarantees sum of orthogonal codes to have constant amplitude. The precoding block in CA-MBCK is a redundant waveform coder whose input bits are generated by processing the information bits. Redundant bits of constant amplitude coded CA-MBCK are not only used to make constant amplitude signal but also used to improve the BER performance at the receiver. In this paper, we proposed a transmission scheme which combines CA-MBCK with $Q^2PSK$ modulation to improve bandwidth efficiency of CA-MBCK and also uses chip interleaving to maintain a constant amplitude feature of CA-MBCK. bandwidth efficiency of a proposed transmission scheme is increased fourfold. And the BER performance of the scheme is same as that of CA-MBCK.

• Journal of Power Electronics
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• v.13 no.3
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• pp.339-348
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• 2013

Multiphase dc-dc converters are widely used in modern power electronics applications due to their advantages over single-phase converters. Such advantages include reduced current stress in both the switching devices and passive elements, reduced output current ripple, and so on. Although the output current ripple of a converter can be significantly reduced by virtue of the interleaving effect, the inductor current ripple cannot be reduced even with the interleaving PWM method. One way to solve this problem is to use a coupled inductor. However, care must be taken in designing the coupled inductor to maximize its performances. In this paper, a detailed analysis of a coupled inductor is conducted and the effect of a coupled inductor on current ripple reduction is investigated extensively. From this analysis, a UU core based coupled inductor structure is proposed to maximize the performance of the coupled inductor.

• Proceedings of the KOSOMBE Conference
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• v.1996 no.11
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• pp.310-313
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• 1996

In this study, we developed three dimensional FDG brain PET and MRI coregistration technique. The boundaries of the head in PET and MRI were segmented using sinogram of emission PET scan and T1-weighted MRI. We registered both boundaries by minimizing the mean Euclidean distance of those. To display the registered PET and MRI simultaneously, we used weighted normalization method and interleaving method.

• ETRI Journal
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• v.40 no.6
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• pp.699-713
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• 2018

Orthogonal frequency division multiplexing (OFDM) has been the overwhelmingly prevalent choice for high-data-rate systems due to its superior advantages compared with other modulation techniques. In contrast, a high peak-to-average-power ratio (PAPR) is considered the fundamental obstacle in OFDM systems since it drives the system to suffer from in-band distortion and out-of-band radiation. The partial transmit sequence (PTS) technique is viewed as one of several strategies that have been suggested to diminish the high PAPR trend. The PTS relies upon dividing an input data sequence into a number of subblocks. Hence, three common types of the subblock segmentation methods have been adopted - interleaving (IL-PTS), adjacent (Ad-PTS), and pseudorandom (PR-PTS). In this study, a new type of subblock division scheme is proposed to improve the PAPR reduction capacity with a low computational complexity. The results indicate that the proposed scheme can enhance the PAPR reduction performance better than the IL-PTS and Ad-PTS schemes. Additionally, the computational complexity of the proposed scheme is lower than that of the PR-PTS and Ad-PTS schemes.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.49 no.7
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• pp.581-588
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• 2021

This paper deals with a beam scheduling method in fighter interleaving mode. Not only the priority of tasks but also operational requirements that air-to-ground and air-to-air search tasks should be executed alternatively are established to maximize high-quality of situational awareness. We propose a real-time heuristic beam scheduling method that is advanced from WMDD to satisfies the requirements. The proposed scheduling method is implemented in a simulation environment resembling the task processing mechanism and measurement model of a radar. Performance improvement in terms of task delay time is observed.

• IEMEK Journal of Embedded Systems and Applications
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• v.17 no.4
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• pp.217-228
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• 2022

Currently, there are increasing demands for applying deep neural networks (DNNs) in the embedded domain such as classification and object detection. The DNN processing in embedded domain often requires custom hardware such as NPU for acceleration due to the constraints in power, performance, and area. Processing DNN models requires a large amount of data, and its seamless transfer to NPU is crucial for performance. In this paper, we developed a cycle-accurate NPU simulator to evaluate diverse NPU microarchitectures. In addition, we propose a novel technique for reducing the number of memory accesses when processing convolutional layers in convolutional neural networks (CNNs) on the NPU. The main idea is to reuse data with memory interleaving, which recycles the overlapping data between previous and current input windows. Data memory interleaving makes it possible to quickly read consecutive data in unaligned locations. We implemented the proposed technique to the cycle-accurate NPU simulator and measured the performance with LeNet-5, VGGNet-16, and ResNet-50. The experiment shows up to 2.08x speedup in processing one convolutional layer, compared to the baseline.

• Journal of IKEEE
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• v.19 no.2
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• pp.168-175
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• 2015

In this paper, we propose FPGA design technique for rotating LED display device which is capable of displaying videos with the use of the afterimage effect. The proposed technique is made up of image data correction process based on inverse gamma correction and error diffusion, block interleaving process, and data serial output process. The data correction process based on inverse gamma correction and error diffusion is an image data correction step in which image data received are corrected by inverse gamma correction process to convert the data into linear brightness characteristics, and by error diffusion process to reduce the brightness reduction phenomenon in low-gray-level which is caused by inverse gamma correction. In the block interleaving process, the data of the frames entered transversely are first saved in accordance with entrance order, and then only the longitudinal image data are read. The data serial output process is applied to convert the parallel data in a rotating location into serial data and send them to LED Driver IC, in order to send data which will be displayed on high-speedy rotating LED Bar. To evaluate the accuracy of the proposed FPGA design technique, this paper used XC6SLX45-FG484, a Spartan 6 family of Xilinx, as FPGA, and ISE 14.5 as a design tool. According to the evaluation analysis, it was found that goal values were consistent with simulation values in terms of accurate operation of inverse gamma and error diffusion correction, block interleaving operation, and serialized operation of image data.

• Proceedings of the IEEK Conference
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• 2002.07a
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• pp.706-709
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• 2002

This paper describes an effective technique for coding video sequences based on JPEG2000 codec. In the proposed method, multiple frames are combined into one large picture by interleaving each pixel data. A large picture enables images to be coded more efficiently and image quality is improved. A video sequence is efficiently coded by adapting the time correlation of the video sequences to spatial correlation. We demonstrated the effectiveness of this method by encoding video sequences using JPEG2000.