• Journal of Information Processing Systems
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• v.4 no.4
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• pp.133-144
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• 2008

Clusters have become a popular alternative for building high-performance parallel computing systems. Today's high-performance system area network (SAN) protocols such as VIA and IBA significantly reduce user-to-user communication latency by implementing protocol stacks outside of operating system kernel. However, emerging parallel applications require a significant improvement in communication latency. Since the time required for transferring data between host memory and network interface (NI) make up a large portion of overall communication latency, the reduction of data transfer time is crucial for achieving low-latency communication. In this paper, Eager Data Transfer (EDT) mechanism is proposed to reduce the time for data transfers between the host and network interface. The EDT employs cache coherence interface hardware to directly transfer data between the host and NI. An EDT-based network interface was modeled and simulated on the Linux-based, complete system simulation environment, Linux/SimOS. Our simulation results show that the EDT approach significantly reduces the data transfer time compared to DMA-based approaches. The EDTbased NI attains 17% to 38% reduction in user-to-user message time compared to the cache-coherent DMA-based NIs for a range of message sizes (64 bytes${\sim}$4 Kbytes) in a SAN environment.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.5 no.4
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• pp.306-317
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• 1995

Abstract Gallium arsenide crystal is usually grown from the melt by the horizontal Bridgman method. We constructed pseudo - steady - state model for crystal growth of GaAs which inclue melt, crystal and the free interface. Mathematical equations of the model were solved for flow, temperature, and concentration field in the melt and temperature field in the crystal. The location and shape of the interface were also solved simultaneously. In 2 - dimensional model, the shape of the interface is flat with adiabatic thermal boundary condition, but it becomes curved with completely conducting thermal boundary condition. In 3 - dimensional model, the interface is less curved than 2 - dimensional case and the flow intensity is similar to that of 2 - dimensional case. With the increase of flow intensity vertical segregation shows maximum value in both 2 - and 3 - D model. However, the maximum value occurs in lower flow intensity in 2 - D model because the interface is more curved for the same flow intensity.

• Tribology and Lubricants
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• v.11 no.4
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• pp.21-27
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• 1995

The effects of interface boundary strength on wear and wear transition during sliding have been investigated in silicon carbide ceramics. Three different microstructures, i.e., solid state sintered silicon carbide, liquid phase sintered silicon carbide and liquid phase sintered silicon carbide composite reinforced with TiB$_{2}$ particulates, were designed by hot pressing. Examinations of crack patterns and fracture modes indicated that interface boundaries were relatively strong between silicon carbide grains in the solid state sintered silicon carbide, intermediate in the liquid phase sintered silicon carbide and weak between silicon carbide grains and TiB$_{2}$ particles in the composite. Wear data and examinations of worn surfaces revealed that the wear behavior of these silicon carbide ceramics could be significantly affected by the interface strength. In the solid state sintered silicon carbide, the wear occurred by a grooving process. In the liquid phase sintered silicon carbide and composite, on the other hand, an abrupt transition in wear mechanism from initial grooving to grain pull-out process occurred during the test. The transition occurred significantly earlier in the composite than in the carbide.

• Journal of the Korean Institute of Intelligent Systems
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• v.27 no.1
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• pp.35-41
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• 2017

This paper presents the development of a monitoring and control system for a vehicle cluster using a model-based design technique. For MBD(model-based design), MATLAB GUI(Graphic User Interface), M programs, simulink, state flow, and tool boxes are used to monitor a number of data such as warning, interrupts, and etc. connected to a real vehicle cluster. As a monitoring tool, a PC(Personal Computer) station interworks with the real vehicle cluster through the interface commands of tool boxes. Thus, unlike existing text-based designs, the MBD based vehicle cluster system provides very easy algorithm updates and addition, since it offers a number of blocks and state flow programs for each functional actions. Furthermore, the proposed MBD technique reduces the required time and cost for the development and modification of a vehicle cluster, because of verification and validation of the cluster algorithm on the monitor through a PC.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.25 no.12
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• pp.1914-1919
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• 2021

With the development of advanced industries, research on image processing hardware is essential, and timing verification at the gate level is required for actual chip operation. For FPGA-based verification, DDR3 memory interface was previously applied. But recently, as the FPGA specification has improved, DDR4 memory is used. In this case, when a previously used memory interface is applied, the timing mismatch of signals may occur and thus cannot be used. This is due to the difference in performance between CPU and memory. In this paper, the problem is solved through state optimization of the existing interface system FSM. In this process, data read speed is doubled through AXI Data Width modification. For actual case analysis, ZC706 using DDR3 memory and ZCU106 using DDR4 memory among Xilinx's SoC boards are used.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.328.1-328.1
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• 2014

MOSFET degradation의 대부분은 hot-carrier injection에 의한 interface state (Dit)의 생성에서 비롯되며 따라서 본 연구에서는 신뢰성에 대한 한 가지 방법으로 Charge pumping method를 이용하여 MOSFET의 interface trap(Dit)의 변화를 측정하였다. 소스와 드레인을 ground로 묶고 게이트에 펄스를 인가한 후 Icp를 측정하여 Dit를 추출하였다. 온도를 293~343 K까지 5 K씩 가변했을 때 293K의 Icp(${\mu}A$)는 0.12 nA 313 K는 0.112 nA 343 K는 0.926 nA이며 Dit (cm-1/eV-1)는 $1.61{\times}10^{12}$ (Cm-2/eV-1) $1.49{\times}10^{12}$ (Cm-2/eV-1) $1.23{\times}10^{12}$ (Cm-2/eV-1)이다. 측정결과 Dit는 Icp가 높은 지점에서 추출되며 온도가 높아지게 되면 Icp전류가 낮아지고 Dit가 줄어드는 것을 볼 수 있다. 온도가 올라가게 되면 carrier들이 trap 준위에서 conduction band 위쪽에 이동하게 되어서 interface에 trap되는 양이 작아지게 된다. 그래서 이때 Icp를 이용해 추출한 Dit 는 실제로 trap의 양이 줄어든 것이 아니라 Thermal excess 현상으로 인해 측정되는 Icp의 양이 줄어든 것으로 분석할 수 있다.

• Journal of the Korean Operations Research and Management Science Society
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• v.17 no.2
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• pp.45-54
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• 1992

It become increasingly important to design user interface to carry low complexity. The cognitive limitations of users severely restrict utility of highly intelligent but complex modern systems. Since humans are known to use schemas to reduce cognitive complexity, imposing good consistency to an interface design that may help that user form useful schemas will provide powerful control over the complexity. This present a research effort to develop a quantitative method for evaluating interface complexity that the user would experience planning his or her course of action. Taking into account the user's potential schemas, a quantitative measure based on information theory was develped to assess the navigational complexity. This approach does not rely on the subjective judgment of the researcher as most schemes dealing with user schemas do. The proposed method may benefit the rapid prototyping approach to design a better user interface by allowing handy assessment of the design.

• Journal of Power System Engineering
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• v.14 no.3
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• pp.52-57
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• 2010

Interlaminar stresses near the free edges of composite laminates have been analyzed considering wall effects. Interface modeling of bonding layer was introduced to explain the wall effect. Using Lekhnitskii stress functions and the principle of complementary virtual work, the interlaminar stresses were obtained, which satisfied the traction free boundary conditions not only at the free edges, but also at the top and bottom surfaces of laminates. The interface modeling provides not singular stresses but concentrated finite interlaminar stresses. The significant amount of reductions of stresses at the free edge are observed compared to the results without interface modeling. The real stress state can be predicted accurately and the results demonstrate the usefulness of the proposed interface modeling for the strength design of composite laminates.

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.50 no.2
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• pp.83-89
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• 2001

This paper introduces a power flow model of SSSC for voltage stability analysis of power system installed with Static Synchronous Compensators. The SSSC model is obtained from the injection model of voltage source inverter by adding the condition that SSSC injection voltage is in quadrature with current of SSSC-installed branch. This model is incorporated into modified CPF algorithm to study effects of SSSC on the security-constrained interface flow limit. Determination of interface flow limit is simply briefed. In case study a 771-bus real system is used to show that interface flow limit can be improved by appropriate control of SSSC in terms of voltage stability.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.11a
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• pp.93-93
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• 2007

We present a mechanism for stress-induced interface degrdadations through ab initio pseudopotential calculations. We find that N interstitials at the interface create various defects levels in the Si band gap, which range from the mid gap to the conduction band of Si. The level positions are dependent on the configuration of oxygen toms around the N interstitial. On the other hand, the mid-gap level caused by Pb center is possibly removed by substitution of a N atom for a threefold-coordinated Si atom in the defect. Our calculations explain why interface state generations are enhanced in Si oxynitride, especially near conduction band edge of Si, although densities of Pb center are reduced.