• Proceedings of the Korean Vacuum Society Conference
• /
• 2012.02a
• /
• pp.331-331
• /
• 2012

With the NAND Flash scaling down, it becomes more and more difficult to follow Moore's law to continue the scaling due to physical limitations. Recently, three-dimensional (3D) flash memories have introduced as an ideal solution for ultra-high-density data storage. In 3D flash memory, as the process reason, we need to use poly-Si TFTs instead of conventional transistors. So, after combining charge trap flash (CTF) structure and poly-Si TFTs, the emerging device SONOS-TFTs has also suffered from some reliability problem such as hot carrier degradation, charge-trapping-induced parasitic capacitance and resistance which both create interface traps. Charge pumping method is a useful tool to investigate the degradation phenomenon related to interface trap creation. However, the curves for charge pumping current in SONOS TFTs were far from ideal, which previously due to the fabrication process or some unknown traps. It needs an optimization and the important geometrical effect should be eliminated. In spite of its importance, it is still not deeply studied. In our work, base-level sweep model was applied in SONOS TFTs, and the nonideal charge pumping current was optimized by adjusting the gate pulse transition time. As a result, after the optimizing, an improved charge pumping current curve is obtained.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2007.11a
• /
• pp.94-95
• /
• 2007

In this paper, the dependence of electrical characteristics of Silicon-$Al_2O_3$-Nitride-Oxide-Silicon (SANOS) memory cell transistors and program speed, reliability of memory device on interface trap between Si substrate and tunneling oxide was investigated. The devices were fabricated by the identical processing in a single lot except the deposition method of the charge trapping layer, nitride. In the case of P/E speed, it was shown that P/E speed is slower in the SONOS cell transistors with larger interface trap density by charge blocking effect, which is confirmed by simulation results. However, the data retention characteristics show much less dependence on interface trap. Therefore, to improve SANOS memory characteristic, it is very important to optimize the interface trap and charge trapping layer.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2008.06a
• /
• pp.373-374
• /
• 2008

Insulating polymers and their composites have been widely used in various electric apparatus or cables. Recently, the effects of interfaces (metal/insulator or insulator/insulator interfaces) on electrical insulation have attracted much attention. However, interfacial phenomena in actual insulation systems and their physical backgrounds are not well understood yet. In this paper, the behaviour of charge carriers near the metal/polymer interface and its effects on conduction and breakdown phenomena are discussed. The metal/polymer interface strongly affects carrier injection, space charge formation and breakdown phenomena. Based on their experimental results, the physical backgrounds of the interfacial phenomena are explained.

• Korean Journal of Computational Design and Engineering
• /
• v.15 no.4
• /
• pp.279-288
• /
• 2010

In this paper, a DEVS(Discrete EVent Systems Specification)-HLA(High Level Architecture) interface was developed in order to perform the simulation using the combined discrete event and discrete time simulation model architecture in a distributed environment. The developed interface connects the combined simulation model with the HLA/RTI(Run-Time Infrastructure) which is an international standard middleware for distributed simulation. The interface consists of an interface model, a model interpreter, and a distributed environment interpreter. The interface model was defined by using the combined simulation architecture in order to easily connect the existing combined simulation model without modification with the HLA/RTI. The model interpreter takes charge of data transmission between the interface model and the combined simulation model. The distributed environment interpreter takes charge of data transmission between the interface model and the HLA/RTI. To evaluate the applicability of the developed interface, it was applied to the diving simulation of a submarine in a distributed environment. The result shows that a simulation result in a distributed environment using the interface is the same to the result in a single computing environment.

• 한국신재생에너지학회:학술대회논문집
• /
• 2007.11a
• /
• pp.274-274
• /
• 2007

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2001.07a
• /
• pp.897-900
• /
• 2001

Space charge distributions in silane crosslinked polyethylene (SXLPE)/ crosslinked polyethylene (XLPE) laminates was investigated using a pulsed electroacoustic (PEA) method. XLPE shows heterocharge while SXLPE shows homocharge. Positive charge is accumulated at the interface of SXLPE/XLPE laminate when applied electric field is more than 20 kV/mm. The charge profile at various temperatures was also acquired using temperature-controllable PEA system. Although applied electric field is only 8.6 kV/mm, positive interfacial charge starts to appear near 50$^{\circ}C$.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2010.02a
• /
• pp.357-357
• /
• 2010

Using ab initio density functional theory, we study the structural and electronic properties of interface between Cu surface and highly electron withdrawing hexaazatriphenylene-hexanitrile (HAT-CN) known as an efficient hole injection layer for organic light emitting diodes (OLEDs). We calculate the equilibrium geometries of the interface with different HAT-CN coverages. Usually, some of C-N bonds located at the edge of the HAT-CN molecule are deformed toward Cu atoms resulting in the reconstruction of Cu surface. By analyzing the electron charge and the potential distributions over the interface, we observe the formation of surface dipoles, which modify the work function at the interface. Such dipole formation is attributed to two origins, one of which is a geometrical nature and the other is a bond dipole. The former is related to structural deformation mentioned above, whereas the latter is due to charge transfer between organic and metal surface.

• Journal of Adhesion and Interface
• /
• v.20 no.4
• /
• pp.155-161
• /
• 2019

Understanding charge transport anisotropy at the interface of conjugated nanostructures basically gives insight into structure-property relationship in organic field-effect transistors (OFET). Here, the anisotropy of the field-effect mobility at the interface between 6,13-bis(triisopropylsilylethynyl) pentacene (TIPS-pentacene) single crystal with cofacial molecular stacks in a-b basal plane and SiO gate dielectric was investigated. A solvent exchange method has been used in order for TIPS-pentacene single crystals to be grown on the surface of SiO₂ thin film, corresponding to the charge accumulation at the interface in OFET structure. In TIPS-pentacene OFET, the anisotropy ratio between the highest and lowest measured mobility is revealed to be 5.2. By analyzing the interaction of a conjugated unit in TIPS-pentacene with the nearest neighbor units, the mobility anisotropy can be rationalized by differences in HOMO-level coupling and hopping routes of charge carriers. The theoretical estimation of anisotropy based on HOMO-level coupling is also consistent with the experimental result.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 1996.11a
• /
• pp.287-290
• /
• 1996

The behaviour of interfacial charge in EPDM/XLPE laminates has been investigated by measuring charge distributions using a pulsed electroacoustic (PEA) method. Homocharge develops in EPDM while heterocharge develops in XLPE. A broadly interfacial charge peak is observed at EPDM/XLPE interface. When EPDM /XLPE laminates are treated in high temperature for different times, the amount and polarity of interfacial charge are changed.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.19 no.12
• /
• pp.2899-2904
• /
• 2015

This paper introduces about the effect on $I_{DS}-V_{GS}$ characteristic of transistor that interface trap charge is created by damage due to heat in a 3D sequential inverter. A interface trap charge distribution in oxide layer in a 3D sequential inverter is extracted using two-dimensional device simulator. The variation of threshold voltage of top transistor according to the gate voltage variation of bottom transistor is also described in terms of Inter Layer Dielectric (ILD) length of 3D sequential inverter, considering the extracted interface trap charge distribution. The extracted interface trap density distribution shows that the bottom $HfO_2$ layer and both the bottom and top $SiO_2$ layer were relatively more affected by heat than the top $HfO_2$ layer with latest process. The threshold voltage variations of the shorter length of ILD in 3D sequential inverter under 50nm is higher than those over 50nm. The $V_{th}$ variation considering the interface trap charge distribution changes less than that excluding it.