• 한국진공학회:학술대회논문집
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• 한국진공학회 2012년도 제42회 동계 정기 학술대회 초록집
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• pp.331-331
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• 2012

With the NAND Flash scaling down, it becomes more and more difficult to follow Moore's law to continue the scaling due to physical limitations. Recently, three-dimensional (3D) flash memories have introduced as an ideal solution for ultra-high-density data storage. In 3D flash memory, as the process reason, we need to use poly-Si TFTs instead of conventional transistors. So, after combining charge trap flash (CTF) structure and poly-Si TFTs, the emerging device SONOS-TFTs has also suffered from some reliability problem such as hot carrier degradation, charge-trapping-induced parasitic capacitance and resistance which both create interface traps. Charge pumping method is a useful tool to investigate the degradation phenomenon related to interface trap creation. However, the curves for charge pumping current in SONOS TFTs were far from ideal, which previously due to the fabrication process or some unknown traps. It needs an optimization and the important geometrical effect should be eliminated. In spite of its importance, it is still not deeply studied. In our work, base-level sweep model was applied in SONOS TFTs, and the nonideal charge pumping current was optimized by adjusting the gate pulse transition time. As a result, after the optimizing, an improved charge pumping current curve is obtained.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2007년도 추계학술대회 논문집
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• pp.94-95
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• 2007

In this paper, the dependence of electrical characteristics of Silicon-$Al_2O_3$-Nitride-Oxide-Silicon (SANOS) memory cell transistors and program speed, reliability of memory device on interface trap between Si substrate and tunneling oxide was investigated. The devices were fabricated by the identical processing in a single lot except the deposition method of the charge trapping layer, nitride. In the case of P/E speed, it was shown that P/E speed is slower in the SONOS cell transistors with larger interface trap density by charge blocking effect, which is confirmed by simulation results. However, the data retention characteristics show much less dependence on interface trap. Therefore, to improve SANOS memory characteristic, it is very important to optimize the interface trap and charge trapping layer.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 하계학술대회 논문집 Vol.9
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• pp.373-374
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• 2008

Insulating polymers and their composites have been widely used in various electric apparatus or cables. Recently, the effects of interfaces (metal/insulator or insulator/insulator interfaces) on electrical insulation have attracted much attention. However, interfacial phenomena in actual insulation systems and their physical backgrounds are not well understood yet. In this paper, the behaviour of charge carriers near the metal/polymer interface and its effects on conduction and breakdown phenomena are discussed. The metal/polymer interface strongly affects carrier injection, space charge formation and breakdown phenomena. Based on their experimental results, the physical backgrounds of the interfacial phenomena are explained.

• 한국CDE학회논문집
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• 제15권4호
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• pp.279-288
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• 2010

In this paper, a DEVS(Discrete EVent Systems Specification)-HLA(High Level Architecture) interface was developed in order to perform the simulation using the combined discrete event and discrete time simulation model architecture in a distributed environment. The developed interface connects the combined simulation model with the HLA/RTI(Run-Time Infrastructure) which is an international standard middleware for distributed simulation. The interface consists of an interface model, a model interpreter, and a distributed environment interpreter. The interface model was defined by using the combined simulation architecture in order to easily connect the existing combined simulation model without modification with the HLA/RTI. The model interpreter takes charge of data transmission between the interface model and the combined simulation model. The distributed environment interpreter takes charge of data transmission between the interface model and the HLA/RTI. To evaluate the applicability of the developed interface, it was applied to the diving simulation of a submarine in a distributed environment. The result shows that a simulation result in a distributed environment using the interface is the same to the result in a single computing environment.

• 한국신재생에너지학회:학술대회논문집
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• 한국신재생에너지학회 2007년도 추계학술대회 논문집
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• pp.274-274
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• 2007

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2001년도 하계학술대회 논문집
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• pp.897-900
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• 2001

Space charge distributions in silane crosslinked polyethylene (SXLPE)/ crosslinked polyethylene (XLPE) laminates was investigated using a pulsed electroacoustic (PEA) method. XLPE shows heterocharge while SXLPE shows homocharge. Positive charge is accumulated at the interface of SXLPE/XLPE laminate when applied electric field is more than 20 kV/mm. The charge profile at various temperatures was also acquired using temperature-controllable PEA system. Although applied electric field is only 8.6 kV/mm, positive interfacial charge starts to appear near 50$^{\circ}C$.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2009년도 제38회 동계학술대회 초록집
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• pp.357-357
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• 2010

Using ab initio density functional theory, we study the structural and electronic properties of interface between Cu surface and highly electron withdrawing hexaazatriphenylene-hexanitrile (HAT-CN) known as an efficient hole injection layer for organic light emitting diodes (OLEDs). We calculate the equilibrium geometries of the interface with different HAT-CN coverages. Usually, some of C-N bonds located at the edge of the HAT-CN molecule are deformed toward Cu atoms resulting in the reconstruction of Cu surface. By analyzing the electron charge and the potential distributions over the interface, we observe the formation of surface dipoles, which modify the work function at the interface. Such dipole formation is attributed to two origins, one of which is a geometrical nature and the other is a bond dipole. The former is related to structural deformation mentioned above, whereas the latter is due to charge transfer between organic and metal surface.

• 접착 및 계면
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• 제20권4호
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• pp.155-161
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• 2019

공액분자 나노구조체 계면에서의 전하이동 이방성을 이해하는 것은 유기전계효과트랜지스터(OFET)에서 구조-물성 상관관계를 규명하는데 중요하다. 본 연구에서는 대표적인 코페이셜 적층구조를 가진 6,13-bis(triisopropylsilylethynyl) pentacene (TIPS-pentacene) 유기반도체 단결정과 산화물 계면에서 전하이동도 이방성을 연구하였다. 용매치환공정을 이용해 유기단결정을 산화실리콘 절연체 표면에 성장시키고 유기단결정/산화물 계면에서 전하이동을 유도할 수 있도록 OFET 소자를 완성하였다. TIPS-pentacene OFET에서 최고/최저 전하이동도 이방성은 5.2로 관찰되었다. TIPS-pentacene의 전하이동을 담당하는 공액부의 최인접부와의 상호작용을 분석한 결과, HOMO 준위 커플링과 전하의 호핑 궤도가 전하이동도 이방성에 기여하는 것으로 밝혀졌다. HOMO 준위 커플링에 기반한 전하이동도 이방성의 정량적 예측은 실험결과와 유사하게 나타났다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1996년도 추계학술대회 논문집
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• pp.287-290
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• 1996

The behaviour of interfacial charge in EPDM/XLPE laminates has been investigated by measuring charge distributions using a pulsed electroacoustic (PEA) method. Homocharge develops in EPDM while heterocharge develops in XLPE. A broadly interfacial charge peak is observed at EPDM/XLPE interface. When EPDM /XLPE laminates are treated in high temperature for different times, the amount and polarity of interfacial charge are changed.

• 한국정보통신학회논문지
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• 제19권12호
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• pp.2899-2904
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• 2015

3차원 순차적 집적회로에서 열에 의한 손상으로 생성되는 계면 포획 전하가 트랜지스터의 드레인 전류-게이트 전압 특성에 미치는 영향을 소개한다. 2차원 소자 시뮬레이터를 이용해서 산화막 층에 계면 포획 전자 분포를 추출한 결과를 설명한다. 이 계면 포획 전자분포를 고려한 3차원 순차적 집적회로에서 Inter Layer Dielectric (ILD)의 길이에 따른 하층 트랜지스터의 게이트 전압의 변화에 따라서 상층 트랜지스터의 문턱전압 $V_{th}$의 변화량에 대해서 소개한다. 상대적으로 더 늦은 공정인 상층 $HfO_2$층 보다 하층 $HfO_2$층과 양쪽 $SiO_2$층이 열에 의한 영향을 더 많이 받았다. 계면 포획 전하 밀도 분포를 사용하지 않았을 때 보다 사용 했을 때 $V_{th}$ 변화량이 더 적게 변하는 것을 확인 했다. 3차원 순차적 인버터에서 ILD의 길이가 50nm이하로 짧아질수록 점점 더 $V_{th}$ 변화량이 급격히 증가하였다.