• Journal of Broadcast Engineering
• /
• v.23 no.5
• /
• pp.606-613
• /
• 2018

This study is concerned with implementing an external memory expansion device for large-scale image processing. It consists of an external memory adapter card with a PCI(Peripheral Component Interconnect) Express Gen3 x8 interface mounted on a graphics workstation for image processing and an external memory board with external DDR(Dual Data Rate) memory. The connection between the memory adapter card and the external memory board is made through the optical interface. In order to access the external memory, both Programmable I/O and DMA(Direct Memory Access) methods can be used to efficiently transmit and receive image data. We implemented the result of this study using the boards equipped with Altera Stratix V FPGA(Field Programmable Gate Array) and 40G optical transceiver and the test result shows 1.6GB/s bandwidth performance.. It can handle one channel of 4K UHD(Ultra High Density) image. We will continue our study in the future for showing bandwidth of 3GB/s or more.

• Journal of the Korean Solar Energy Society
• /
• v.38 no.1
• /
• pp.45-55
• /
• 2018

Environmentally benign lead-free solder coated ribbon (e. g. SnCu, SnZn, SnBi${\cdots}$) has been intensively studied to interconnect cells without lead mixed ribbon (e. g. SnPb) in the crystalline silicon(c-Si) photovoltaic modules. However, high melting point (> $200^{\circ}C$) of non-lead based solder provokes increased thermo-mechanical stress during its soldering process, which causes early degradation of PV module with it. Hence, we proposed low-temperature conductive paste (CP) based tabbing method for lead-free ribbon. Modules, interconnected by the lead-free solder (SnCu) employing CP approach, exhibits similar output without increased resistivity losses at initial condition, in comparison with traditional high temperature soldering method. Moreover, 400 cycles (2,000 hour) of thermal cycle test reveals that the module integrated by CP approach withstands thermo-mechanical stress. Furthermore, this approach guarantees strong mechanical adhesion (peel strength of ~ 2 N) between cell and lead-free ribbons. Therefore, the CP based tabbing process for lead free ribbons enables to interconnect cells in c-Si PV module, without deteriorating its performance.

• Design & Manufacturing
• /
• v.6 no.1
• /
• pp.95-100
• /
• 2012

In this study, a novel Cu composite sheet with embedded high electric conduction path was developed as another alternative for the interconnect materials possessing high electrical conductivity as well as high strength. The Cu composite sheet was fabricated by forming Ag conduction paths not within the interior but on the surface of a high strength Cu substrate by damascene electroplating process. As a result, the electrical conductivity increased by 40% thanks to mesh type Ag conduction paths, while the ultimate tensile strength decreased by 20%. The interfacial fracture resistance of Cu composite sheet prepared by damascene electroplating increased by above 50 times compared to Cu composite sheet by conventional electroplating. For feasibility test for practical application, a leadframe for LED module was manufactured by a progressive blanking and piercing processes, and the blanked surface profile was evaluated as a function of the volume fraction of Ag conduction paths. As Ag conduction path became finer, pressing formability improved.

• Journal of the Korean Operations Research and Management Science Society
• /
• v.30 no.4
• /
• pp.151-161
• /
• 2005

For Internet service providers (ISPs), there are three common types of interconnection agreements : private peering, public peering and transit. One of the most important problems for a single ISP is to determine which other ISPs to interconnect with, and under which agreements. The problem can be then to find a set of private peering providers, transit providers and Internet exchanges (IXs) when the following input data are assumed to be given : a set of BGP addresses with traffic demands, and a set of potential service providers (Private peering/transit providers and IXs) with routing information, cost functions and capacities. The objective is to minimize the total interconnection cost. We show that the problem is NP-hard, give a mixed-integer programming model, and propose a heuristic algorithm. Computational experience with a set of test instances shows the remarkable performance of the proposed algorithm of rapidly generating near-optimal solutions.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2002.07a
• /
• pp.18-21
• /
• 2002

As the mask design rules get smaller, the probability of the process failure becomes higher due to the narrow overlay margin between the contact and metal interconnect layers. To obtain the minimum process margin, a tabbing and cutting method is applied with the rule based optical proximity correction to the metal layer, so that the protection to bridge problems caused by the insufficient space margin between the metal layers can be accomplished. The side-lobe phenomenon from the attenuated phase shift mask with the tight design nile is analyzed through the aerial image simulation for test patterns with variation of the process parameters such as numerical aperture, transmission rate, and partial coherence. The corrected patterns are finally generated by the rules extracted from the side-lobe simulation.

• Proceedings of the IEEK Conference
• /
• 2002.06b
• /
• pp.209-212
• /
• 2002

As the mask design rules get smaller, the probability of the process failure becomes higher doc to the narrow overlay margin between the contact and metal interconnect layers. To obtain the minimum process margin, a tabbing and cutting method Is applied with the rule based optical\ulcorner proximity correction to the metal layer, so that the protection to bridge problems caused by the insufficient space margin between the metal layers can be accomplished. The side-lobe phenomenon from the attenuated phase shift mask with the tight design rule is analyzed through the aerial image simulation for test patterns with variation of the process parameters such as numerical aperture, transmission rate, and partial coherence. The corrected patterns are finally generated by the rules extracted from the side-lobe simulation.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.39 no.1
• /
• pp.67-75
• /
• 2002

In this Paper, we discuss the PEEC method and construct the PEEC equivalent circuit of the test structure and construct the system matrix, which was simulated by numerical analysis. And we got node voltages and currents. Constructing the equivalent circuit, we extracted the parasitic parameter(R, L, C)using the simulator, which is based on finite element method, hence we could simulate the transient analysis.

• Journal of Welding and Joining
• /
• v.32 no.3
• /
• pp.53-59
• /
• 2014

The mechanical stability of solder joints in electronic devices with Sn-Ag-Cu is a continuous issue since the material was applied to the industry. Various shock test methods were developed and standardized tests are used in the industry worldwide. Although it is applied for several years, the detailed mechanism of the shock induced failure mechanism is still under investigation. In this study, the effect of external temperature was observed on large Flip-chip BGA components. The weight and size of the large package produced a high strain region near the corner of the component and thus show full fracture at around 200G level shock input. The shock performance at elevated temperature, at $100^{\circ}C$ showed degradation based on board pad designs. The failure mode and potential failure mechanisms are discussed.

• The Transactions of the Korean Institute of Electrical Engineers C
• /
• v.49 no.8
• /
• pp.433-437
• /
• 2000

We fabricated switch module of ATM(Asynchronous Transfer Mode) exchange system with MCM-C(MultiChip Module Co-fired) technology and measured its electrical characteristics. Green tape was used as substrate and Au/Ag paste was used to form the interconnect layers. The via holes were made by drill and filled with metal paste usign screen method. After manufacturing the substrate, chips and passive components were assembled on the substrate. In electrical test, the module showed the output signal of 46.9MHz synchronized with input signal. In the view of substrate size reduction, the area of MCM switch module was 35% of conventional hybrid switch module.

• Journal of the Korean Institute of Telematics and Electronics C
• /
• v.34C no.2
• /
• pp.38-49
• /
• 1997

In this paper, w describe partitioning large circuits into multiple chips on the programmable FPCB for rapid prototyping. FPCBs consists of areas for FPGAs for logic and interconnect components, and the routing topology among them are predetermined. In the partition problem for FPCBs, the number of wires ofr routing among chips is fixed, which is an additonal constraints to the conventional partition problem. In order to deal with such aconstraint properly we first define a new partition problem, so called the topologybased partition problem, and then propose a heuristic method. The heuristic method is based on the simulated annealing and clustering technique. The multi-level tree clustering technique is used to obtain faster and better prtition results. In the experimental results for several test circuits, the restrictions for FPCB were all satisfied and the needed execution time was about twice the modified K-way partition method for large circuits.