• JSTS:Journal of Semiconductor Technology and Science
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• v.9 no.1
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• pp.8-13
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• 2009

In this paper, discontinuous interconnect lines are modeled as a cascaded line composed of many uniform interconnect lines. The system functions of respective uniform interconnect lines are determined, followed by its time domain response. Since the time domain response expression is a transcendental form, the waveform expression is reconfigured as an approximated linear expression. The proposed model has less than 2% error in the delay estimation.

• KIPS Transactions on Computer and Communication Systems
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• v.8 no.3
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• pp.65-72
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• 2019

HPC(High Performance Computing) is the computing system that connects a number of computing nodes with high performance interconnect network. In the HPC, interconnect network technology is one of the key player to make high performance systems, and mainly, Infiniband or Ethernet are used for interconnect network technology. Nowadays, PCIe interface is main interface within computer system in that host CPU connects high performance peripheral devices through PCIe bridge interface. For connecting between two computing nodes, PCIe Non-Transparent Bridge(NTB) standard can be used, however it basically connects only two hosts with its original standards. To give cost-effective interconnect network interface with PCIe technology, we develop a prototype of interconnect network system with PCIe NTB. In the prototyped system, computing nodes are connected to each other via PCIe NTB interface constructing switchless interconnect network such as ring network. Also, we have implemented prototyped data sharing mechanism on the prototyped interconnect network system. The designed PCIe NTB-based interconnect network system is cost-effective as well as it provides competitive data transferring bandwidth within the interconnect network.

• Nuclear Engineering and Technology
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• v.17 no.4
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• pp.290-301
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• 1985

600MW(e) CANDU Primary Heat Transport System (PHTS) is composed of the two “figure-of-eight” loops and is designed to operate with the 4% Reactor Outlet Header (ROH) quality at its rated power. This existence of the two compressible regions and the positive flow-qualitly-void feedbacks are the sources of the PHTS flow instability. To ensure the PHTS stability, ROH-ROH interconnect pipes are installed as passive systems. This paper describes the investigation of the PHTS flow instability at its design full power condition. Also studied are the interconnect effect and the inherent system damping effect on the system stability. The time domain stability analyses are accessed by using the ATHER/MOD-I code which is the improved version of the KAERI developed ATHER code. Under the most adverse system modelling, the “figure-of-eight” symmetric loop shows divergent flow oscillations. Under with the interconnect, the PHTS stability is remarkably enhanced so that the system becomes stable. However, even under the conservative pressurizer modelling, the PHTS shows the more convergent flow oscillations. With the interconnect and the pressurizer modelling, its stability is highly credited. Conclusively, the inherent system damping by pressurizer itself can credit the PHTS stability without the interconnect.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.9
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• pp.114-120
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• 1995

It is important to test the various kinds of interconnect faults between chips on a card/module. When boundary scan design techniques are adopted, the chip to chip interconnection test generation and application of test patterns is greatly simplified. Various test generation algorithms have been developed for interconnect faults. A new interconnect test generation algorithm is introduced. It reduces the number of test patterns by half over present techniques. It also guarantees the complete diagnosis of mutiple interconnect faults.

• Clean Technology
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• v.16 no.4
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• pp.297-303
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• 2010

Effect of interconnect structure on the cell performance in anode-supported tubular solid oxide fuel cell (SOFC) has been investigated in this study, employing the Fluent CFD solver. For the robust and reliable theoretical analysis corroborating experimental results, it is of great importance to elucidate the role of interconnect which is electrically connected with electrodes on the cell characteristics. From the fact that the thin interconnect provides the enhanced cell performance, it is revealed that the interconnect thickness is a key parameter that is able to effectively control the ohmic resistance. Under the constant thickness condition, the cell performance does not considerably change with the variation of interconnect width. This is because the current passage along with circumferential direction is not effectively altered by the change of interconnect width in tubular SOFC system.

• ETRI Journal
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• v.45 no.5
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• pp.910-921
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• 2023

In this study, we designed a 6T-SRAM cell using 16-nm CMOS process and analyzed the performance in terms of read-speed latency. The temperaturedependent Cu and multilayered graphene nanoribbon (MLGNR)-based nanointerconnect materials is used throughout the circuit (primarily bit/bit-bars [red lines] and word lines [write lines]). Here, the read speed analysis is performed with four different chip operating temperatures (150K, 250K, 350K, and 450K) using both Cu and graphene nanoribbon (GNR) nano-interconnects with different interconnect lengths (from 10 ㎛ to 100 ㎛), for reading-0 and reading-1 operations. To execute the reading operation, the CMOS technology, that is, the16-nm PTM-HPC model, and the16-nm interconnect technology, that is, ITRS-13, are used in this application. The complete design is simulated using TSPICE simulation tools (by Mentor Graphics). The read speed latency increases rapidly as interconnect length increases for both Cu and GNR interconnects. However, the Cu interconnect has three to six times more latency than the GNR. In addition, we observe that the reading speed latency for the GNR interconnect is ~10.29 ns for wide temperature variations (150K to 450K), whereas the reading speed latency for the Cu interconnect varies between ~32 ns and 65 ns for the same temperature ranges. The above analysis is useful for the design of next generation, high-speed memories using different nano-interconnect materials.

• Journal of the Microelectronics and Packaging Society
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• v.4 no.2
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• pp.25-32
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• 1997

대용량, 고속 정보처리가 요구되는 System의 모듈은 Data 처리의 고속성 및 회로의 고집적이 가능한 MCM의 형태로 구현되어 ATM, GPS 및 PCS 등의 분야에 광범위하게 응 용되고 있다. 위와 같은 High Speed 응용분야에서의 System 성능은 Interconnect Line의 전달지연, 임피던스 부정합에 의한 신호 반사 손실. 신호선 간의 Crosstalk, Ground Bounce 등의 현상에 대한 최적화 여부에 결정적인 영향을 받는다. 그러나 Interconnect의 특성상 정 형이 존재하지 않으므로 추상적인 Library를 구축하는 형식으로 접근할 수밖에 없으며 이를 위하여 여러기본 구조를 정의한후 각 Dimension을 변수로 두고 해석 결과를 합성하여 Database화하는 접근방식이다. 본 논문에서는 MCM-D 공정을 이용하여 Interconnect Line 특성을 분석하고 Database화 하기 위한 Test Pattern을 구현하고 Time Domain reflectometry(TDR)을 이용하여 그특성들을 측정 분석하였다. Test pattern 제작은 MCM-D 공정으로 최소선폭 27$\mu$m, Via Hole 75$\mu$m으로 형성하였고 2 Layer Signal과 GND로 총 3Layer를 구현하였다. 특성분석을 위해 TDR장비와 모데링 및 Simulation S/W인 IPA 510 을 사용하였다. 이를 통해 MCM-D를 이용한 공정에서 Interconcet Line의 고주파 특성을 측정하고 정량화하여 LIbrary를 제작할수 있었다.

• Proceedings of the KIEE Conference
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• 2005.07c
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• pp.2357-2359
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• 2005

In this paper, we analyzed the effect of flip chip interconnect which is a part of FC-BGA package on the transmission characteristics of interconnect. We designed simple interconnect model and analyzed the change of the transmission characteristics as the size of each component change. And we provided design guide of interconnect which shows more enhanced results.

• Journal of Information Processing Systems
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• v.18 no.1
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• pp.159-172
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• 2022

The role of the interconnect network, which connects computing nodes to each other, is important in high-performance computing (HPC) systems. In recent years, the peripheral component interconnect express (PCIe) has become a promising interface as an interconnection network for high-performance and cost-effective HPC systems having the features of non-transparent bridge (NTB) technologies. OpenSHMEM is a programming model for distributed shared memory that supports a partitioned global address space (PGAS). Currently, little work has been done to develop the OpenSHMEM library for PCIe-interconnected HPC systems. This paper introduces a prototype implementation of the OpenSHMEM library through a switchless interconnect network using PCIe NTB to provide a PGAS programming model. In particular, multi-interrupt, multi-thread-based data transfer over the OpenSHMEM shared memory model is applied at the implementation level to reduce the latency and increase the throughput of the switchless ring network system. The implemented OpenSHMEM programming model over the PCIe NTB switchless interconnection network provides a feasible, cost-effective HPC system with a PGAS programming model.

• Journal of IKEEE
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• v.27 no.3
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• pp.355-367
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• 2023

Local Interconnect Network (LIN) is a low-speed in-vehicle network bus, and it is widely used in body applications such as windows, doors, HVAC, and lighting. This review explains protocols and message frames of LIN bus in detail. LIN bus basically transmits ID and payloads in data frame. How to interpret ID and payloads is defined in LIN Description file (LDF). Each LIN bus has unique LDF and its corresponding unique configuration. This review also explains syntax and example of LDF in detail.