• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.13 no.10
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• pp.812-816
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• 2000

It is very important to understand the correlation of between inter dielectric(ILD) CMP process and various facility factors supplied to equipment to equipment system. In this paper, the correlation between the various facility factors supplied to CMP equipment system and ILD-CMP process was studied. To prevent the partial over-polishing(edge hot-spot) generated in the wafer edge area during polishing, we analyze various facilities supplied at supply system. With facility shortage of D.I water(DIW) pressure, we introduced an adding purified $N_2$(P$N_2$)gas in polishing head cleaning station for increasing a cleaning effect. DIW pressure and P$N_2$gas factors were not related with removal rate, but edge hot-spot of patterned wafer had a serious relation. We estimated two factors (DIW pressure and P$N_2$gas) for the improvement of CMP process. Especially, we obtained a uniform planarity in patterned wafer and prohibited more than 90% wafer edge over-polishing. In this study, we acknowledged that facility factors supplied to equipment system played an important role in ILD-CMP process.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.04b
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• pp.31-34
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• 2000

It is very important to understand the correlation of between inter layer dielectric(ILD) CMP process and various facility factors supplied to equipment system. In this paper, the correlation between the various facility factors supplied to CMP equipment system and ILD CMP process were studied. To prevent the partial over-polishing(edge hot-spot) generated in the wafer edge area during polishing, we analyzed various facilities supplied at supply system. With facility shortage of D.I. water(DIW) pressure, we introduced an adding purified $N_2(PN_2)$ gas in polishing head cleaning station for increasing a cleaning effect. DIW pressure and PN2 gas factors were not related with removal rate, but edge hot-spot of patterned wafer had a serious relation. We estimated two factors (DIW pressure and PN2 gas) for the improvement of CMP process. Especially, we obtained a uniform planarity in patterned wafer and prohibited more than 90% wafer edge over-polishing. In this study, we acknowledged that facility factors supplied to equipment system played an important role in ILD-CMP process.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.05b
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• pp.30-33
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• 2001

Chemical mechanical polishing(CMP) process has been widely used to planarize dielectrics, which can apply to employed in integrated circuits for sub-micron technology. Despite the increased use of CMP process, it is difficult to accomplish the global planarization of free-defects in inter-level dielectrics (ILD). Especially, defects like micro-scratch lead to severe circuit failure, and affects yield. CMP slurries can contain particles exceeding $1{\mu}m$ size, which could cause micro-scratch on the wafer surface. The large particles in these slurries may be caused by particle agglomeration in slurry supply line. To reduce these defects, slurry filtration method has been recommended in oxide CMP. In this work, we have studied the effects of filtration and the defect trend as a function of polished wafer count using various filters in inter-metal dielectric(IMD)-CMP. The filter installation in CMP polisher could reduce defect after IMD-CMP. As a result of micro-scratches formation, it shows that slurry filter plays an important role in determining consumable pad lifetime.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.14 no.7
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• pp.557-561
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• 2001

Chemical mechanical polishing (CMP) process has been widely used to planarize dielectric layers, which can be applied to the integraded circuits for sub-micron technology. Despite the increased use of CMP process, it is difficult to accomplish the global planarization of in the defect-free inter-level dielectrics (ILD). Especially, defects such as micro-scratch lead to severe circuit failure which affect yield. CMP slurries can contain particles exceeding 1㎛ in size, which could cause micro-scratch on the wafer surface. The large particles in these slurries may be caused by particles agglomeration in slurry supply line. To reduce these defects, slurry filtration method has been recommended in oxide CMP. In this work, we have studied the effects of filtration and the defect trend as a function of polished wafer count using various filters in inter-metal dielectrics(IMD)-CMP process. The filter installation in CMP polisher could reduce defects after IMD-CMP process. As a result of micro-scratch formation, it is shown that slurry filter plays an important role in determining consumable pad lifetime. The filter lifetime is dominated by the defects. We have concluded that slurry filter lifetime is fixed by the degree of generating defects.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.51 no.7
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• pp.311-315
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• 2002

Chemical mechanical polishing (CMP) process was required for the global planarization of inter-metal dielectric(IMD), inter-level dielectric (ILD) layers of multi-layer interconnections. In this paper, we studied the characteristics of polishing pad, which can apply shallow trench isolation (STI)-CMP process for global planarization of multi-level interconnection structure. Also, we investigated the effects of different sets of polishing pad, such as soft and hard pad. As an experimental result, hard pad showed center-fast type, and soft pad showed edge-fast type. Totally, the defect level has shown little difference, however, the counts of scratch was detected less than 2 on JR111 pad. Through the above results, we can select optimum polishing pad, so we can expect the improvements of throughput and device yield.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.05c
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• pp.149-153
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• 2003

Chemical mechanical polishing (CMP) technology for global planarization of multi-level inter-connection structure has been widely studied for the next generation devices. CMP process has been paid attention to planarized pre-metal dielectric (PMD), inter-layer dielectric (ILD) interconnections. Expecially, shallow trench isolation (STI) used to CMP process on essential. Recently, the direct STI-CMP process without the conventional complex reverse moat etch process has established by using slurry additive with the high selectivity between $SiO_2$ and $Si_3N_4$ films for the purpose of process simplification and n-situ end point detection(EPD). However, STI-CMP process has various defects such as nitride residue, tom oxide and damage of silicon active region. To solve these problems, in this paper, we studied the planarization characteristics using a high selectivity slurry(HSS). As our experimental results, it was possible to achieve a global planarization and STI-CMP process could be dramatically simplified. Also we estimated the reliability through the repeated tests with the optimized process conditions in order to identify the reproducibility of HSS STI-CMP process.

• Proceedings of the Materials Research Society of Korea Conference
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• 2011.10a
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• pp.23-23
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• 2011

Chemical-Mechanical Planarization (CMP) 공정이란 화학적 반응 및 기계적인 힘이 복합적으로 작용하여 표면을 평탄화하는 공정이다. 이러한 CMP 공정은 반도체 산업에서 회로의 고집적화와 다층구조를 형성하기 위하여 도입되었으며 반도체 제조를 위한 필수공정으로 그 중요성이 강조되고 있다. 특히 최근에는 Inter-Level Dielectric (ILD)의 형성과 Shallow Trench Isolation (STI) 공정에서실리콘 산화막을 평탄화하기 위한 CMP 공정에 대해 연구가 활발히 이루어지고 있다. 그러나 CMP 공정 후 scratch, pitting corrosion, contamination 등의 Defect가 발생하는 문제점이 존재한다. 이 중에서도 scratch는 기계적, 열적 스트레스에 의해 생성된 패드의 잔해, 슬러리의 잔유물, 응집된 입자 등에 의해 표면에 형성된다. 반도체 공정에서는 다양한 종류의 실리콘 산화막이 사용되고 gks이러한 실리콘 산화막들은 종류에 따라 경도가 다르다. 따라서 실리콘 산화막의 경도에 따른 CMP 공정 및 이로 인한 Scratch 발생에 관한 연구가 필요하다고 할 수 있다. 본 연구에서는 scratch 형성의 거동을 알아보기 위하여 boronphoshposilicate glass (BPSG), plasma enhanced chemical vapor deposition (PECVD) tetraethylorthosilicate (TEOS), high density plasma (HDP) oxide의 3가지 실리콘 산화막의 기계적 성질 및 이에 따른 CMP 공정에 대한 평가를 실시하였다. CMP 공정 후 효율적인 scratch 평가를 위해 브러시를 이용하여 1차 세정을 실시하였으며 습식세정방법(SC-1, DHF)으로 마무리 하였다. Scratch 개수는 Particle counter (Surfscan6200, KLA Tencor, USA)로 측정하였고, 광학현미경을 이용하여 형태를 관찰하였다. Scratch 평가를 위한 CMP 공정은 실험에 사용된 3가지 종류의 실리콘 산화막들의 경도가 서로 다르기 때문에 동등한 실험조건 설정을 위해 동일한 연마량이 관찰되는 조건에서 실시하였다. 실험결과 scratch 종류는 그 형태에 따라 chatter/line/rolling type의 3가지로 분류되었다 BPSG가 다른 종류의 실리콘 산화막에 비해 많은 수에 scratch가 관찰되었으며 line type이 많은 비율을 차지한다는 것을 확인하였다. 또한 CMP 공정에서 압력이 증가함에 따라 chatter type scratch의 길이는 짧아지고 폭이 넓어지는 것을 확인하였다. 본 연구를 통해 실리콘 산화막의 경도에 따른 scratch 형성 원리를 파악하였다.

• Proceedings of the KIEE Conference
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• 2004.07c
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• pp.1727-1729
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• 2004

Chemical mechanical polishing (CMP) process has been widely used to planarize dielectric layers, which can be applied to the integrated circuits for sub-micron technology. Despite the increased use of CMP precess, it is difficult to accomplish the global planarization of in the defect-free inter-level dielectrics (ILD). we investigated the performance of $WO_3$ CMP used silica slurry, ceria slurry, tungsten slurry. In this paper, the effects of addition oxidizer on the $WO_3$ CMP characteristics were investigated to obtain the higher removal rate and lower non-uniformity.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.04b
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• pp.89-92
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• 2004

Chemical mechanical polishing (CMP) process has been widely used to planarize dielectric layers, which can be applied to the integrated circuits for sub-micron technology. Despite the increased use of CMP process, it is difficult to accomplish the global planarization of in the defect-free inter-level dielectrics (ILD). we investigated the performance of $WO_3$ CMP used silica slurry, ceria slurry, tungsten slurry. In this paper, the effects of addition oxidizer on the $WO_3$ CMP characteristics were investigated to obtain the higher removal rate and lower non-uniformity.

• Proceedings of the KSME Conference
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• 2003.11a
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• pp.922-927
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• 2003

In this paper, slurry fluid motion, abrasive particle motion, and roles of groove patterns on the pads are numerically investigated in the 2D and 3D geometries. The simulation results are analyzed in terms of experimental removal rate and WIWNU (within wafer non-uniformity) for ILD (inter level dielectric) CMP process. Numerical investigations reveal that the grooves in the pad behave as uniform distributor of abrasive particles and enhance the removal rate by increasing shear stress. Higher removal rate and desirable uniformity are numerically and experimentally observed at the pad with grooves. Numerical analysis is very well matched with experimental results and helpful for understanding polishing mechanism and local physics.