• Proceedings of the KIPE Conference
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• 2016.11a
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• pp.123-124
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• 2016

LLC 컨버터는 동작범위에 따라 특성이 바뀌는 전달함수로 인해 제어기 설계와 최적화에 어려움이 따른다. 본 논문에서는 이를 해결하기 위해 새로운 방식의 전하제어를 제안한다. 먼저, 소신호 등가모델을 분석해 공진 캐패시터 전압이 공진 전류와 같은 위상을 가진다는 것을 보인 후, 캐패시터가 resettable integrator가 될 수 있음을 밝힌다. 이를 바탕으로 디지털 구현에 적합한 전하제어를 제안한다. 그리고 실험을 바탕으로 제안한 제어의 타당성을 검증한다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.10
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• pp.1957-1964
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• 1994

In this thesis, a Synthetic Aperture Rarar Processor that is possible real-time handling is implemented using CW(Continuose Wave) laser as a light source, CCD(charge Coupled Device) as a time integrator, and AOD(Acousto-Optic Device) as the space integrator. One of the advantages of the proposed system is that it does not require driving circuits of the light source. To implement the system, the linear frequency modulation(chirp) technique has been used for radar signal. The received data for the unit target was processed using 7.80 board and accompanying electronic circuits. In order to reduce the smear effect of the focused chirp signal which occurs Bragg diffrection angle of the AOD has been utilized to make sharp pulses of the laser source, and the pulse made synchronized with the chirp signal. Experiment and analysis results of the data and images detected from CCD of the proposed SAR system demonstrated that detection effect is degrated as the unit target distance increases, and the resolving power is improved as the bandwidth of the chirp signal increases. Also, as the pulse width of the light source decreases, the smear effect has been reduced. The experimental results assured that the proposed system in this papre can be used as a real time SAR processor.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.23 no.5
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• pp.1310-1318
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• 1998

Sigma-delta converter is frequently used for conyerting low-frequency anglog to digital signal. The converter consists of a modulator and a digital filer, but our work is concentrated on the modulator. In this works, to design second-order sigma-dalta modulator with 14bit resolution, we define maximumerror limits of each components (operational smplifier, integrator, internal ADC, and DAC) of modulator. It is first performed modeling of an ideal second-order sigma-delta modulator. This is then modified by adding the non-ideal factors such as limit of op-amp output swing, the finit DC gain of op-amp slew rate, the integrator gian error by the capacitor mismatch, the ADC error by the cmparator offset and the mismatch of resistor string, and the non-linear of DAC. From this modeling, as it is determined the specification of each devices requeired in design and the fabrication error limits, we can see the final performance of modulator.

• The Proceeding of the Korean Institute of Electromagnetic Engineering and Science
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• v.10 no.3
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• pp.2-17
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• 1999

Interpolated second order polynomials(ISOP's) are proposed to design efficient cascaded integrator-comb(CIC)-based decimation filters for a programmable downconverter. It is shown that some simple ISOP's can effectively reduce the passband droop caused by CIC filtering with little degradation in aliasing attenuation. In addition, ISOP's are shown to be useful for simplifying halfband filters that usually follow CIC filtering. As a result, a modified half band filter(MHBF) is introduced which is simpler than conventional halfband filters. The proposed decimation filter for a programmable downconverter is a cascade of a CIC filter, an ISOP, MHBF's and a programmable finite impulse response(FIR) filter. A procedure for designing the decimation filter is developed. In particular, an optimization technique that simultaneously designs the decimation filter is developed. In particular, an optimization technique that simultaneously designs the ISOP and programmable FIR filters is presented. Design examples demonstrate that the proposed method leads to more efficient programmable downconverters than existing ones.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.37 no.4
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• pp.28-34
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• 2000

In this paper, a continuous-time filter for low voltage and high frequency applications using fully-balanced current integrators is presented. As the balanced structure of integrator circuits, the designed filter has improved noise characteristics and wide dynamic range since even-order harmonics are cancelled and the input signal range is doubled. Using complementary current mirrors, bias circuits are simplified and the cutoff frequency of filters can be controlled easily by a single DC bias current. As a design example, the 3rd-order lowpass Butterworth filter with a leapfrog realization is designed. The designed fully-balanced current-mode filter is simulated and examined by SPICE using 0.65${\mu}{\textrm}{m}$ CMOS n-well process parameters. The simulation results show 50MHz cutoff frequency, 69㏈ dynamic range with 1% total harmonic distortion(THD), and 4㎽ power dissipation with a 3V supply voltage.

• KOREAN JOURNAL OF PACKAGING SCIENCE & TECHNOLOGY
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• v.20 no.3
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• pp.91-96
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• 2014

TTI was applied to monitor the quality changes of fish displayed at a mock store. Chilled fishes were displayed with TTI on a styrofoam box filled with crushed ice. The ice was periodically refilled to maintain the fish freshness. The color of TTI and the qualities of mackerel and Alaska pollack were measured during displaying. VBN and Pseudomonas spp. were used as the quality factors of mackerel and Pollack, respectively. The spoilage time was regarded as when the factors reached their critical levels. The fishes were spoiled when the color of TTI reached an end-point. It was therefore found out that it is possible to predict the fish spoilage by observing the TTI color change.

• Journal of Sensor Science and Technology
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• v.6 no.2
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• pp.115-122
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• 1997

In this paper, on-chp atomatic tuning circuit, using proposed integration level approximation technique, is designed to tuning of the variation of RC time-constant due to aging or temperature variation, etc. This circuit reduces the error, the difference between code values and real outputs of integrator, which is drawback of presented dual-slope tuning circuit and eliminates modulations of processing signals in integrated circuit due to fixed tuning codes during ordinary operation. This system is made up of simple integrator, A/D converter and digital control circuit and all capacitors are replaced by programed capacitor arrays in this system. This tuning circuit with 4 bit resolution achieves $-9.74{\sim}+9.68%$ of RC time constant error for 50% resistance variation.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.11
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• pp.141-148
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• 2012

A design of a 32-bit fourth-stage decimation filter decimation filter used in sigma-delta analog-to-digital (A/D) converter is proposed in this work. A four-stage decimation filter with down-sampling factor of 512 and 32-bit output is developed. A multi-stage cascaded integrator-comb (CIC) filter, which reduces the sampling rate by 64, is used in the first stage. Three half-band FIR filters are used after the CIC filter, each of which reduces the sampling rate by two. The pipeline structure is applied in the CIC filter to reduce the power consumption of the CIC. The Canonic Signed Digit (CSD) arithmetic is used to optimize the multiplier structure of the FIR filter. This filter is implemented based on a semi-custom design flow and a 130nm CMOS standard cell library. This decimation filter operates at 98.304 MHz and provides 32-bit output data at an audio frequency of 192 kHz with power consumption of $697{\mu}W$. In comparison to the previous work, this design shows a higher performance in resolution, operation frequency and decimation factor with lower power consumption and small logic utilization.

• Journal of IKEEE
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• v.19 no.1
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• pp.87-93
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• 2015

In this paper, a $145{\mu}W$, 87dB SNR, Low power 3rd order Sigma-Delta Modulator with Op-amp sharing is proposed. Conventional architecture with analog path and digital path is improved by adding a delayed feed -forward path for disadvantages that coefficient value of the first integrator is small. Proposed architecture has a larger coefficient value of the first integrator to remove the digital path. Power consumption of proposed architecture using op-amp sharing is lower than conventional architecture. Simulation results for the proposed SDM designed in $0.18{\mu}m$ CMOS technology with power supply voltage 1.8V, signal bandwidth 20KHz and sampling frequency 2.8224MHz shows SNR(Signal to Noise Ratio) of 87dB, the power consumption of $145{\mu}W$.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.36 no.7
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• pp.712-718
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• 2008

This paper deals with a development of flight control law switching system which can be used for flight test of the research control law by switching control law during flight. Through this research program, fader logic and integrator stabilization design has been introduced to minimize the transient response of aircraft caused by flight control law switching and to prevent the divergence of the integrator included in the control law in standby mode. MIL-STD-1553B communication was applied to transfer the data between the two control laws. This paper introduce the control law switching system architecture and major design concept and include the system verification and validation result performed on the flying quality simulator of the advanced trainer.