• 대한기계학회논문집A
• /
• 제31권8호
• /
• pp.826-832
• /
• 2007

Fully flexible cell preserves Hamiltonian in structure so that the symplectic time integrator is applicable to the equations of motion. In the direct formulation of fully flexible cell N-Sigma-T ensemble, a generalized leapfrog time integration (GLF) is applicable for fully flexible cell simulation, but the equations of motion by GLF has structure of implicit algorithm. In this paper, the time integration formula is derived for the fully flexible cell molecular dynamics simulation by using the splitting time integration. It separates flexible cell Hamiltonian into terms corresponding to each of Hamiltonian term. Thus the simple and completely explicit recursion formula was obtained. We compare the performance and the result of present splitting time integration with those of the implicit generalized leapfrog time integration.

• 한국정보통신학회논문지
• /
• 제6권6호
• /
• pp.891-896
• /
• 2002

본 논문에서는 저전압 동작이 가능하도록 완전차동 구조의 적분기에 전압조절을 위한 튜닝회로를 추가하여 새로운 적분기를 제안하였다. 제안된 적분기는 이득과 주파수 더 나아가 응용회로의 특성에 영향을 주는 트랜스컨덕턴스값을 증가시키기 위해 전류미러 방식을 이용하여 구성되었다. HSPICE 시뮬레이션 결과, 제안된 적분기는 기존의 완전자동 구조의 적분기에 비해 그 이득값이 두 배 이상 향상되었으며, 간단한 전압조절을 통한 이득 및 주파수 조절이 가능하였다.

• 한국통신학회논문지
• /
• 제25권10B호
• /
• pp.1785-1792
• /
• 2000

In this paper multi-rate non-recursive architecture for CIC(Cascaded Integrator-Comb) decimation filters with an arbitrary factor is proposed. The CIC filters are widely used in high speed wireless communication systems since they have multiplier-less and multi-rate low-power structure. Even conventional non-recursive CIC structure is multi-rate this architecture can be structured only in case of M-th power-of-two decimation factor. This paper proposes that muli-rate non-recursive CIC architecture can be structured with an any decimation factor of product form. Power consumption of the proposed architecture is compared with that of the conventional non-recursion architecture.

• 한국통신학회논문지
• /
• 제21권7호
• /
• pp.1726-1733
• /
• 1996

A 3V-50MHz analog CMOS continuous-time current-mode filter with a negative resistance load(NRL) is proposed. In order to design a current-mode current integrator, a modified basic current mirror with a NRL to increase the output resistance is employed. the inherent circuit structure of the designed NRL current integrator, which minimizes the internal circuit nodes and enhances the gain bandwidth product, is capable of making the filter operate at the high frequency. The third order Butterworth low pass filter utilizing the designed NRL current integrator is synthesized and simulated with a 1.5.mu.m CMOS n-well proess. Simulation result shows the cutoff frequency of 50MHz and power consumption of 2.4mW/pole with a 3V power supply.

• 전기학회논문지
• /
• 제60권4호
• /
• pp.871-876
• /
• 2011

In this paper, a voltage-controlled frequency tunable current-mode integrator and a 3rd-order current-mode Chebyshev filter in 1.8V-$0.18{\mu}m$ CMOS is realized for software radio applications in system-on-chips. This filter is used for reconstruction purposes between a current-steering DAC and a current-mode mixer. Power consumption of the designed filter can be reduced by using a current-mode small size integrator. And also, cutoff frequency of this filter is variable between 1.2MHz and 10.1MHz, the power consumption is 2.85mW. And the voltage bias compensated circuit is used to control the voltage variation.in the designed filter.

• 대한전자공학회논문지
• /
• 제23권3호
• /
• pp.409-414
• /
• 1986

To eliminate the requirement of multiplications in nonrecursive filter realization, the use of a delta modulation(DM) has been studied by several researchers. However, the structure of DM filters inevitably contains an intergrator that is cascaded with the arithmetic unit to operate convolution summation. In this paper we porpose a method to determine the coefficients that may be used for implementation of a DM filter without an integrator. Also, we obtain the condition by which one can exclude the response errors due to the elimination of the integrator. By computer simulations it is shown that the performance of the proposed filter is very good, providing that the condition is satisfied.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 1988년도 추계학술대회 논문집 학회본부
• /
• pp.465-468
• /
• 1988

A n-well CMOS Operational Transconductance Amplifier -C(OTA-C) integrator with a wide linear input range is designed. The circuit designed has superior linearity of input voltage range compared with the conventional source-coupled pair OTA. The OTA developed in this paper is versatile in application: diverse applications are in the fields of linear amplifiers, continuous-time filters, gain control circuits, and analog multipliers, etc..

• 대한전자공학회논문지
• /
• 제15권4호
• /
• pp.20-25
• /
• 1978

능동 RC 여파회로 설계에 보상 적분기와 가산 증폭기를 사용하였다. 두개의 보상 적분기를 기본회로망(메모리 소자)으로 하고 여기에 세개의 단자를 인출하여 적당한 가산 증폭기 만을 연결하므로써 평면의 좌반면에 복소수 pole을 가지는 2계 전달함수를 구현할 수 있다.

• 제어로봇시스템학회:학술대회논문집
• /
• 제어로봇시스템학회 2000년도 제15차 학술회의논문집
• /
• pp.237-237
• /
• 2000

In this paper, The modified dead-time compensator for plants with an integrator and long dead time is proposed. The design procedure takes account of the closed-loop performance and robustness. The tuning of the controller can be done using some information about the plant and its uncertainties. The proposed controller is compared to others recently presented in the literature. Some simulation results verify good closed-performance and robustness of the proposed DTC.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 1998년도 하계학술대회 논문집 A
• /
• pp.61-63
• /
• 1998

A B-H curve measuring system for testing softmagnetic materials was constructed. This system can measure the B-H curve in the low frequency(0.1 - 1 Hz) range. The drift of the integrator can be moderately removed by software technique. The advantages of the developed system are easier to measure B-H curve compared with conventional measuring system and low cost.