• Journal of Power Electronics
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• 제12권6호
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• pp.878-885
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• 2012

A new sustainer with primary-side integration of DC/DC converters and energy recovery(SPIDER) circuits is proposed. The proposed circuit operates as a DC-DC converter during address period and energy recovery circuit during sustain period. Therefore, the conventional three electronic circuits composed of the power supply, X-driver, and Y-driver can be reduced to one circuit. As a result, it has desirable advantages such as a simple structure, less mass, fewer devices and cost reduction. Moreover, since the Zero Voltage Switching (ZVS) of all power switches can be guaranteed, a switching loss can be considerably decreased. To confirm the operation, validity, and features of the proposed circuit, experimental results from a prototype for 42-inch PDP are presented.

• 한국재료학회:학술대회논문집
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• 한국재료학회 1992년도 추계학술발표강연 및 논문개요집
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• pp.61-61
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• 1992

• 한국전자파학회지:전자파기술
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• 제22권1호
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• pp.42-51
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• 2011

• 전자공학회지
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• 제14권1호
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• pp.56-63
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• 1987

• 한국진공학회:학술대회논문집
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• 한국진공학회 1994년도 제7회 학술발표회 및 한·일 CVD 심포지움 논문개요집
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• pp.75-75
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• 1994

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2008년도 International Meeting on Information Display
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• pp.692-695
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• 2008

Large area emissive displays have problems with nonuniform pixel characteristics and their individual ageing. A pixel integrated driver with pixel based optical feedback is presented to solve these problems. Photodetectors, optical feedback circuit and data handling capabilities are integrated in a high voltage CMOS technology.

• Journal of Magnetics
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• 제19권3호
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• pp.295-299
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• 2014

Recently, module-integrated converter (MIC) research has shown interest in small-scale photovoltaic (PV) generation. The converter is capable of efficient power generation. In this system, the high frequency transformer should be made compact, and demonstrate high efficiency characteristics. This paper presents a core structure optimization procedure to improve the efficiency of a high frequency transformer of compact size. The converter circuit is considered in the finite element analysis (FEA) model, in order to obtain an accurate FEA result. The results are verified by the testing of prototypes.

• ETRI Journal
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• 제30권5호
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• pp.644-652
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• 2008

In this paper, a low-power CMOS interface circuit is designed and demonstrated for capacitive sensor applications, which is implemented using a standard 0.35-${\mu}m$ CMOS logic technology. To achieve low-power performance, the low-voltage capacitance-to-pulse-width converter based on a self-reset operation at a supply voltage of 1.5 V is designed and incorporated into a new interface circuit. Moreover, the external pulse signal for the reset operation is made unnecessary by the employment of the self-reset operation. At a low supply voltage of 1.5 V, the new circuit requires a total power consumption of 0.47 mW with ultra-low power dissipation of 157 ${\mu}W$ of the interface-circuit core. These results demonstrate that the new interface circuit with self-reset operation successfully reduces power consumption. In addition, a prototype wireless sensor-module with the proposed circuit is successfully implemented for practical applications. Consequently, the new CMOS interface circuit can be used for the sensor applications in ubiquitous sensor networks, where low-power performance is essential.

• ETRI Journal
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• 제38권2호
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• pp.272-279
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• 2016

In this paper, a new structure for an advanced high holding voltage silicon controlled rectifier (AHHVSCR) is proposed. The proposed new structure specifically for an AHHVSCR-based electrostatic discharge (ESD) protection circuit can protect integrated circuits from ESD stress. The new structure involves the insertion of a PMOS into an AHHVSCR so as to prevent a state of latch-up from occurring due to a low holding voltage. We use a TACD simulation to conduct a comparative analysis of three types of circuit - (i) an AHHVSCR-based ESD protection circuit having the proposed new structure (that is, a PMOS inserted into the AHHVSCR), (ii) a standard AHHVSCR-based ESD protection circuit, and (iii) a standard HHVSCR-based ESD protection circuit. A circuit having the proposed new structure is fabricated using $0.18{\mu}m$ Bipolar-CMOS-DMOS technology. The fabricated circuit is also evaluated using Transmission-Line Pulse measurements to confirm its electrical characteristics, and human-body model and machine model tests are used to confirm its robustness. The fabricated circuit has a holding voltage of 18.78 V and a second breakdown current of more than 8 A.

• 한국정보통신학회논문지
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• 제13권6호
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• pp.1117-1122
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• 2009

본 논문에서는 온도 센서 및 온도 측정을 위한 제어회로를 설계하였다. 설계된 회로는 기존의 방법들과는 달리 일반적인 CMOS(Complementary Metal Oxide Semiconductor) 공정에서 추가 공정없이 제작 가능하도록 설계하였으며, 온도는 디지털 값으로 출력 되도록 구성하였다. 설계되어진 회로는 5volts 공급전압을 사용하였으며, 0.5${\mu}m$ CMOS 공정을 사용하였다. 온도 측정을 위한 회로는 PWM(Pulse Width Modulation) 제어회로, VCO(Voltage controlled oscillator), 카운터 그리고 레지스터로 구성되어 있다. PWM 제어회로의 동작 주파수는 23kHz 이며, VCO의 동작 주파수는 416kHz, 1MHz, 2MHz를 사용하였다. 회로의 동작은 SPICE(Simulation Program with Integrated Circuit Emphasis)를 사용하여 확인 하였다.