• Journal of the Institute of Electronics Engineers of Korea TC
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• v.44 no.2
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• pp.62-68
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• 2007

This paper proposes an efficient integer division algorithm for high speed FPGAs' which support built-in RAMs' and multipliers. The integer division algorithm is iterative with RAM-based LUT and multipliers, which minimizes the usage of logic fabric and connection resources. Compared with some popular division algorithms such as division by subtraction or division by multiply-subtraction, the number of iteration is much smaller, so that very low latency can be achieved with pipelined implementations. We have implemented our algorithm in the Xilinx virtex-4 FPGA with VHDL coding and have achieved 300MSPS data rate in 17bit integer division. The algorithm used less than 1/6 of logic slices, 1/4 of the built-in multiply-accumulation units, and 1/3 of the latencies compared with other popular algorithms.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.41 no.4
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• pp.31-39
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• 2004

The ARM7 TDMI microprocessor employ a software routine iteration method in order to handle integer division operation, but this method has long execution time and many execution instruction. In this paper, we proposed ARM7 TDMI microprocessor with integer division instruction. To make this, we additionally defined UDIV instruction for unsigned integer division operation and SDIV instruction for signed integer division operation, and proposed ARM7 TDMI microprocessor data Path to apply division algorithm. Applied division algorithm is nonrestoring division algorithm and additive hardware is reduced using existent ARM data path. To verify the proposed method, we designed proposed method on RTL level using HDL, and conducted logic simulation. we estimated the number of execution cycles and the number of execution instructions as compared proposed method with a software routine iteration method, and compared with other published integer divider from the number of execution cycles and hardware size.

• IEIE Transactions on Smart Processing and Computing
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• v.6 no.1
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• pp.39-46
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• 2017

In this paper, we propose an integer frequency offset estimation and compensation method based on PLC preamble correlation in DOCSIS 3.1 Downstream system. The proposed method determines the PLC preamble subcarrier location recovered from PLC data and the one obtained from PLC preamble correlation. We showed the performance of PLC preamble detection in the received signal through the maximum value detection of PLC preamble correlation. Thus we can estimate and compensate for the integer frequency offset by computing the difference of PLC subcarrier locations.

• Journal of the Korean Operations Research and Management Science Society
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• v.39 no.1
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• pp.13-27
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• 2014

In this paper, we deal with a Steiner Ring Star (SRS) problem arising from the design of survivable telecommunication networks. We develop two mixed integer programming formulations for the SRS problem by implementing Miller-Tucker-Zemlin (MTZ) and Sarin-Sherali-Bhootra (SSB) subtour elimination constraints, and then apply the reformulation-linearization technique (RLT) to enhance the lower bound obtained by the LP relaxation. By exploiting the ring-star structure of underlying network, we devise some valid inequalities that tighten the LP relaxation. Computational results demonstrate the effectiveness of the proposed solution procedure.

• Proceedings of the IEEK Conference
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• 2003.07d
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• pp.1391-1394
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• 2003

본 논문은 ARM7 TDMI 마이크로프로세서의 연산기능 중 구현되지 알은 나눗셈 연산 기능을 추가로 구현하였다. 이를 위해 ARM ISA(Instruction Set Architecture)에 부호를 고려한 나눗셈 명령어인 'SDIV' 명령어를 추가로 정의하였으며, 나눗셈 알고리즘 Signed Nonrestoring Division을 수행할 수 있도록 ARM7 TDMI 마이크로프로세서의 Data Path를 재 설계하였다. 제안된 방법의 타당성을 검증하기 위하여 현재 ARM7 TDMI 마이크로프로세서의 정수 나눗셈 연산처리 방법과 제안된 구조에서의 정수 나눗셈 연산 처리 방법을 비교하였으며, 그 겉과 수행 cycle의 수가 40％로 감소되는 것을 확인하였다

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.3 no.1
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• pp.31-37
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• 2010

This paper proposes a novel method for pilot-aided integer frequency offset (IFO) estimation in orthogonal frequency division multiplexing (OFDM)-based digital video broadcasting-terrestrial (DVB-T) systems. The conventional method proposed for estimating the IFO uses only partial information of combinations that pilots can provide, which stems from a rigorous assumption that the channel responses of pilots used for estimating the IFO change very rapidly. In this paper, we propose an efficient IFO estimation method exploiting additional information of combinations that pilots can provide to improve the performance of the IFO estimation. The simulation results show that the proposed method outperforms the conventional method in terms of the IFO detection probability.

• Journal of Navigation and Port Research
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• v.39 no.1
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• pp.15-21
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• 2015

In high precision positioning systems based on GNSS, ambiguity resolution is an important procedure. Correct ambiguity leads to positioning results which have high precision between millimeters and centimeters. However, when the ambiguity is determined incorrectly, ensuring accuracy and precision of the positioning result is impossible. An ambiguity validation test is required to obtain correct ambiguity when ambiguity resolution is performed based on the ILS (Integer Least Squares), which shows the best performance in point of theory and experiment when compared with other methods such as IR (Integer Rounding) and IB (Integer Bootstrapping). Comparison between the candidates of the validation test is needed to judge ambiguity correctly, because ILS searches for candidates of integer ambiguity, unlike other methods which calculate only one integer ambiguity. We analyzed the experimental performance of ambiguity validation tests. R-ratio, F-ratio and W-ratio were adopted for analysis. The performance of validation tests was evaluated by classifying normal operation, detection, missed detection and false alarm. As a result, strengths and weaknesses of validation tests was showed to experimental. we concluded that validation tests must be selected according to environment.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.279-282
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• 1999

Frequency divider selects the channel of the frequency synthesizer. General programmable divider has many flip-flops to realize all integer division value and stability problem by using dual modules prescaler. In this paper, a new architecture of programmable divider is proposed and designed to improve these problems. The proposed programmable divider has only thirteen flip-flops. The programmable divider is designed by 0.65${\mu}{\textrm}{m}$ CMOS technology and HSPICE. Operating frequency of the programmable divider is 200MHz with a 3V supply voltage.

• International Journal of Fuzzy Logic and Intelligent Systems
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• v.5 no.3
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• pp.274-279
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• 2005

For high-speed fuzzy control systems, an important problem is the improvement of speed for the fuzzy inference, particularly in the consequent part and the defuzzification stage. This paper introduces an algorithm to map real values of the fuzzy membership functions in the consequent part onto an integer grid, as well as a method of eliminating the unnecessary operations of the zero items in the defuzzification stage, allowing a center of gravity method to be implemented with only integer additions and one integer division. A VHDL implementation of the system is presented. The proposed system shows approximately an order of magnitude increase in speed as compared with conventional methods while introducing only a minimal error and can be used in many fuzzy controller applications.

• Management Science and Financial Engineering
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• v.12 no.1
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• pp.127-142
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• 2006

In this paper, we present a frequency reassignment problem (FRP) that arises when we add new base stations to resolve hot-spots or to expand the coverage of a code division multiple access (CDMA) network. For this problem, we develop an integer programming (IP) model along with some valid inequalities and preprocessing rules. Also, we develop an effective heuristic procedure that solves two sub-problems induced from the original problem in repetition. Computational results show that the proposed heuristic procedure finds a feasible solution of good quality within reasonable computation time. Also, the lower bound by-produced from the heuristic procedure is quite strong.