• Journal of IKEEE
• /
• v.11 no.4
• /
• pp.358-363
• /
• 2007

This paper presents a floating point unit(FPU) with 3 stages for a 3D graphics shader engine. It targeted to accelerate 3D graphics in portable device environments. In order to design a balanced architecture for a shader engine, we analyzed shader assembly instructions and estimated the performance of FPU with the method we propose. The proposed unit handles 4-dimensional data through separated two paths that are lead to general operation module and special function module. The proposed FPU is compiled as a form of the cascade FPU with 3 stages to efficiently handle a matrix operation with relatively low hardware overhead. Except some complex instructions that are executed using macro instructions, all instructions complete an operation in a single instruction cycle at 100MHz frequency. A special function module performs all operations in a single clock cycle using the Newton Raphson method with the look-up table.

• Journal of the Korean Institute of Telematics and Electronics B
• /
• v.32B no.5
• /
• pp.702-709
• /
• 1995

Conditional branch instructions are a major obstacle to the increasing of RISC processor performance, because they can break the smooth flow of instructions; the issuing of instructions after a branch instruction must often wait until the condition is resolved. This paper proposes a hardware scheme which has a duplicated fetching logic to reduce the penalty imposed by conditional branch instructions. The proposed shceme has a buffer to maintain states of processor, which supports the precise interrupt. We make use of two code segments to test the performance and their results were compared with those of the delayed branch. We got the result that the proposed scheme reduces the branch penalty extremely.

• Journal of the Korean Institute of Telematics and Electronics
• /
• v.21 no.1
• /
• pp.57-61
• /
• 1984

This paper deals with the selection of minimal test instruction set for microprocessor data processing test. This test method is based on a function description of the instructions which are obtained from the data given by the user's manual. Selecting procedure is done in 3 steps: 1) a test execution graphs are represented on the instructions which are grouped functionally, 2) the essential graphs, the eliminable graphs, the eliminable graphs, and the eligible graphs are built, 3) optimal test instruction set from the essential graphs and the eligible graphs is defined. In the case of INTEL 8048, 50 test instructions can be selected optimally from 8048 instruction repertories (96 instructions)

• Proceedings of the KIEE Conference
• /
• 2003.11c
• /
• pp.924-927
• /
• 2003

In this paper, we design the memory tester chip set playing an important role in the memory tester as central parts. Memory tester has the sixteen inner instructions to control the test sequence and the address and data signals to DUT. These instructions are saved in memory with each chip such as sequence chip and address/data generator chip. Sequence chip controls the test sequence according to instructions saved in the memory. And Generator chip generates the address and data signals according to instructions saved in the memory, too.

• Proceedings of the KIEE Conference
• /
• 2004.05a
• /
• pp.153-155
• /
• 2004

In this paper, we design the memory tester chip playing an important role in the memory tester as central parts. Memory tester has the sixteen inner instructions to control the test sequence and the address and data signals to DUT. These instructions are saved in memory with each block such as sequencer and pattern generator. Sequencer controls the test sequence according to instructions saved in the memory. And Pattern generator generates the address and data signals according to instructions saved in the memory, too. We can use these chips for various functional test of memory.

• Proceedings of the Korea Information Processing Society Conference
• /
• 2011.04a
• /
• pp.43-45
• /
• 2011

Very Long Instruction Word (VLIW) executes multiple instructions in parallel. In order to exploit higher performance, i.e., higher parallelism, VLIW compiler groups as many instructions into one word as possible. In this paper, we show how to construct a VLIW C compiler based on GCC for CDSP32 (Compact Digital Signal Processor 32-bit) which is an embedded DSP processor to issue two instructions in one VLIW. Also, we evaluated the compiler on EEMBC benchmark; the experiment result showed that the total number of dynamic instructions of the VLIW compiler was reduced by 18% on average over without VLIW instruction scheduling.

• Journal of KIISE:Software and Applications
• /
• v.32 no.8
• /
• pp.819-833
• /
• 2005

Code size reduction is ever becoming more important for compilers targeting embedded processors because these processors are often severely limited by storage constraints and thus the reduced code size can have a positively significant Impact on their performance. Various code size reduction techniques have different motivations and a variety of application contexts utilizing special hardware features of their target processors. In this work, we propose a novel technique that fully utilizes a set of hardware instructions, called the multiple load/store (MLS), that are specially featured for reducing code size by minimizing the number of memory operations in the code. To take advantage of this feature, many microprocessors support the MLS instructions, whereas no existing compilers fully exploit the potential benefit of these instructions but only use them for some limited cases. This is mainly because optimizing memory accesses with MLS instructions for general cases is an NP-hard problem that necessitates complex assignments of registers and memory off-sets for variables in a stack frame. Our technique uses a couple of heuristics to efficiently handle this problem in a polynomial time bound.

• Journal of The Korean Association For Science Education
• /
• v.30 no.2
• /
• pp.249-260
• /
• 2010

The main purpose of this study is to examine the effects of explicit instructions on the nature of science (NOS) on the understanding of science-gifted students. Participants were engaged in 8 explicit NOS instructions spanning 6 months. Data were collected before and after the instructions from 20 science-gifted students using student worksheets, open-ended questionnaires (Views of Nature Of Science, VNOS), and in-depth interviews. The results of this study showed that explicit instructions were helpful in improving the understanding of the tentativeness in science and socially and culturally embedded aspects of science. However, participants not only still possess naive views on the nature of science about the distinction of law and theory and the empirical aspects of science, but also had conflicting views and misconceptions in some areas. The study has implication for development of science-gifted program that the explicit instructions on NOS and science inquiry should be provided concurrently, given the complementary relationship of the two activities.

• Journal of the Korea Society of Computer and Information
• /
• v.17 no.8
• /
• pp.1-10
• /
• 2012

This paper proposes design space exploration methodology of many-core processors including multimedia specific instructions to support high-performance and low power ultrasound imaging for portable devices. To explore the impact of multimedia instructions, we compare programs using multimedia instructions and baseline programs with a same many-core processor in terms of execution time, energy efficiency, and area efficiency. Experimental results using a $256{\times}256$ ultrasound image indicate that programs using multimedia instructions achieve 3.16 times of execution time, 8.13 times of energy efficiency, and 3.16 times of area efficiency over the baseline programs, respectively. Likewise, programs using multimedia instructions outperform the baseline programs using a $240{\times}320$ image (2.16 times of execution time, 4.04 times of energy efficiency, 2.16 times of area efficiency) as well as using a $240{\times}400$ image (2.25 times of execution time, 4.34 times of energy efficiency, 2.25 times of area efficiency). In addition, we explore optimal PE architecture of many-core processors including multimedia instructions by varying the number of PEs and memory size.

• The Korean Journal of Emergency Medical Services
• /
• v.13 no.2
• /
• pp.87-98
• /
• 2009

Purpose : This study set out to compare the educational effects of a video self-instruction program for child CPR education on childcare teachers by applying the 2006 KACPR Guideline. By adopting the nonequivalent control group posttest quasi-experimental design, the study examined the educational effects on a group that did not receive instructions from the instructor, another group that received his instructions, and the other group that received an extra three-minute practice training session in addition to instructions. Methods : Data were gathered from August 6 to 18, 2008. As for research tools, the Knowledge Instrument of CPR by Connolly (2006) was used along with the National Practice Test Protocol for C1ass 1 Emergency Medical Technicians (2007) and Common Protocol for CPR (2006) to examine the performance of child CPR. By shooting the guide screen of $Resusci^{(R)}$ Junior CPR Manikin of Leardal with a video camera and using the Skill Guide Checklist of the Common Protocol for CPR (2006), the subjects' technical accuracy of chi1d CPR was evaluated. There were three subject groups: 29 childcare teachers randomly assigned to received the video self-instruction program training for chi1d CPR and no instructions from the instructor made up the control group; 22 childcare teachers randomly assigned to received the program training and instructions from the instructor made up experiment group I; 23 childcare teachers randomly assigned to received an extra three-minute practice training session in addition to the program training and the instructions made up experiment group II. The gathered data were analyzed with SPSS/PC+ (Version 14.0) in frequency, percentage, $X^2$-test, ANOVA, Scheffe test. Results : 1) There were no statistically significant differences (F=1.030, p=.362) among the groups in terms of knowledge scores after the child CPR education. 2) There were statistically significant differences (F=13.625, p=.000) among the groups in terms of performance abilities after the child CPR education. 3) There were no statistically significant differences (F=1.610, p=.207) among the groups in terms of technical accuracy of mouth-to-mouth resuscitation after the child CPR education 4) There were no statistically significant differences (F=1.484, p=.234) among the groups in terms of technical accuracy of chest compression after the child CPR education. Conclusion : The results indicate that childcare teachers can improve their performance abilities in child CPR when the instructors are active with their instructions and extra practice hours are secured through a VSI program. It's also needed to provide education with increasing concentration ratio about the items of lower knowledge points in order to help the teachers learn the accurate theory of child CPR. And there should be VSI programs of diverse conditions to increase the effects of child CPR training among childcare teachers.