• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.117-120
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• 2001

This paper presents a HW/SW co-design environments and its validation for development of virtual component on the 32-bit RISC core which is used in the design of Information-Appliance-On-a-Chip. For the experimental environment, we developed the cycle-accurate instruction set simulator based on SE3208 RISC core of ADChips. To verify the function of RISC core at the cycle level, we implemented the verification environment by grafting this simulator on the Seamless CVE which is a commercial co-verification environment.

• Journal of KIISE:Computer Systems and Theory
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• v.27 no.8
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• pp.741-751
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• 2000

To achieve high performance by exploiting instruction level parallelism aggressively in superscalar processors, it is necessary to overcome the limitation imposed by control dependences and data dependences which prevent instructions from executing parallel. Value prediction is a technique that breaks data dependences by predicting the outcome of an instruction and executes speculatively its data dependent instruction based on the predicted outcome. In this paper, a hybrid value prediction scheme with dynamic classification mechanism is proposed. We design a hybrid predictor by combining the last predictor, a stride predictor and a two-level predictor. The choice of a predictor for each instruction is determined by a dynamic classification mechanism. This makes each predictor utilized more efficiently than the hybrid predictor without dynamic classification mechanism. To show performance improvements of our scheme, we simulate the SPECint95 benchmark set by using execution-driven simulator. The results show that our scheme effect reduce of 45% hardware cost and 16% prediction accuracy improvements comparing with the conventional hybrid prediction scheme and two-level value prediction scheme.

• Journal of KIISE:Computer Systems and Theory
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• v.28 no.11
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• pp.601-612
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• 2001

In superscalar processors, value prediction is a technique that breaks true data dependences by predicting the outcome of an instruction in order to exploit instruction level parallelism(ILP). A value predictor looks up the prediction table for the prediction value of an instruction in the instruction fetch stage, and updates with the prediction result and the resolved value after the execution of the instruction for the next prediction. However, as the instruction fetch and issue rates are increased, the same instruction is likely to fetch again before is has been updated in the predictor. Hence, the predictor looks up the stale value in the table and this mostly will cause incorrect value predictions. In this paper, a stride value predictor with the capability of speculative updates, which can update the prediction table speculatively without waiting until the instruction has been completed, is proposed. Also, the performance of the scheme is examined using Simplescalar simulator for SPECint95 benchmarks in which our value predictor is added.

• JSTS:Journal of Semiconductor Technology and Science
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• v.5 no.4
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• pp.221-228
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• 2005

In this work, our goal is to develop a fast and accurate power model of the ARM926EJ-S processor in the industrial design environment. Compared with existing work on processor power modeling which focuses on the power states of processor core, our model mostly focuses on the cache power model. It gives more than 93% accuracy and 1600 times speedup compared with post-layout gate-level power estimation. We also address two practical issues in applying the processor power model to the real design environment. One is to incorporate the power model into an existing commercial instruction set simulator. The other is the re-characterization of power model parameters to cope with different gate-level netlists of the processor obtained from different design teams and different fabrication technology.

• The Transactions of the Korea Information Processing Society
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• v.5 no.1
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• pp.202-214
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• 1998

Exploitation of instruction-level parallelism(ILP) is an effective mechanism for improving the performance of modern super-scalar and VLIW processors. Various software techniques can be applied to increase ILP. Among these techniques, predicated execution is the one that increases the degree of ILP by allowing instructions from different basic blocks to be converted to a single basic block by removing branch instructions. In this paper, a global predicate-sensitive scheduling algorithm is proposed to improve the performance for ILP processors that support predicated execution. In order to examine the performance of proposed algorithm, a C compiler and a simulator are developed. By simulating various benchmark programs with the compiler and the simulator, the performance results of this algorithm are measured and the effectiveness of the algorithm is verified. As a result of measure performance with I, 2, 4 issue execution, this study was confirmed average performance by 20% or more.

• Journal of Korean Society of Industrial and Systems Engineering
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• v.24 no.65
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• pp.51-63
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• 2001

The present experiment investigated the possibility of evaluating of the human sensibility contingent on the speed and modes of driving using the responses from the autonomic nervous system, subjective assessments, Simulator Sickness (55) in dynamic simulator. The three conditions of the speed of driving were 40 $\pm$ 10 km/h, 100$\pm$10 km/h, 160 $\pm$ 10 km/h, and the participant was instructed to drive the car for three minutes on the elliptical track. It is programed in such a way that the modes of driving can be changed smoothly using road DB in Dynamic Simulator, and for signifying the change of the condition the road signs were used. The instruction was given to the participant to drive the car on the fixed speed of 20 km/h for 30 seconds, then to drive the car on sudden-start mode of driving from the 20 km/h to 160 km/h within 10 seconds. For the sudden-stop mode of driving, it was instructed that stop the car from the speed of 160km/h to 20km/h within 10 seconds when the subject see the road sign, then drive the car at the fixed speed of 20 km/h for 30 seconds. The results of the subjcetive assessment showed that the level of pleasantness and the tension was increased, and physiological response showed that the level of activity of the autonomic responses were also increased as the speed of the car increased. Also, for results on the driving modes showed that the level of pleasantness was highest for the sudden-stop, next highest was sudden-start, and the lowest was 20 km/h fixed speed condition for the subjective assessment, and tile order of the level of activation of the autonomic nervous system showed the same results as above. From the results of the present study it was concluded that the presentation and evaluation of the stimulus for the human sensitivity is possible in dynamic simulator.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.129-132
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• 2002

AE64000 is the 64-bit high-performance microprocessor that ADC Co. Ltd. is developing for an embedded environment. It has a 5-stage pipeline and uses Havard architecture with a separated instruction and data caches. It also provides SIMD-like DSP and FP operation by enabling the 8/16/32/64-bit MAC operation on 64-bit registers. AE64000 processor implements the EISC ISA and uses the instruction folding mechanism (Instruction Folding Unit) that effectively deals with LERI instruction in EISC ISA. But this unit makes branch prediction behavior difficult. In this paper, we designs a branch predictor optimized for AE64000 Pipeline and develops a AES4000 simulator that has cycle-level precision to validate the performance of the designed branch predictor. We makes TAC(Target address cache) and BPT(branch prediction table) seperated for effective branch prediction and uses the BPT(removed indexed) that has no address tags.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.41 no.6
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• pp.1-11
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• 2004

Modern processors achieve high performance exploiting avaliable Instruction Level Parallelism(ILP) by using speculative technique such as branch prediction. Traditionally, branch direction can be predicted at very high accuracy by 2-level predictor, and branch target address is predicted by Branch Target Buffer(BTB). Except for indirect branch, each of the branch has the unique target, so its prediction is very accurate via BTB. But because indirect branch has dynamically polymorphic target, indirect branch target prediction is very difficult. In general, the technique of branch direction prediction is applied to indirect branch target prediction, and much better accuracy than traditional BTB is obtained for indirect branch. We present a new indirect branch target prediction scheme which combines a indirect branch instruction with its data dependent register of the instruction executed earlier than the branch. The result of SPEC benchmark simulation which are obtained on SimpleScalar simulator shows that the proposed predictor obtains the most perfect prediction accuracy than any other existing scheme.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.7
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• pp.43-52
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• 2004

This paper proposes an efficient functional verification environment of microprocessor. This verification environment consists of test vector generator part, simulator part, and comparator part. To enhance efficiency of verification, it use a bias random test vector generator. In a part of simulation, retargetable instruction level simulator is used for reference model. This verification environment is excellent to find error which is not detected by general test vector and will become a good guide to find new error type

• Journal of the Korea Society for Simulation
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• v.15 no.1
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• pp.35-42
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• 2006

Sensor network, that is an infrastructure of ubiquitous computing, consists of a number of sensor nodes of which hardware is very small. The network topology and routing scheme of the network should be determined according to its purpose, and its hardware and software may have to be changed as needed from time to time. Thus, the sensor network simulator being capable of verifying its behavior and estimating performance is required for better design. Sensor network simulators currently existing have been developed for specific hardwares or operating systems, so that they can only be used for such systems and do not provide any means to estimate the amount of power consumption and program execution time which are major issues for system design. In this study, we develop the sensor network simulator that can be used to design and verify various sensor networks without regarding to types of applications or operating systems, and also has the capability of predicting the amount of power consumption and program execution time. For this purpose, the simulator is developed by using machine instruction-level discrete-event simulation scheme. As a result, the simulator can be used to analyze program execution timings and related system behaviors in the actual sensor nodes in detail. Instruction traces used as workload for simulations are executable images produced by the cross-compiler for ATmega128L microcontroller.