• Proceedings of the IEEK Conference
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• summer
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• pp.204-208
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• 2004

Embedded business will be expanded market more and more since customers seek more wearable and ubiquitous systems. Cellular telephones, PDAs, notebooks and portable multimedia devices could bring higher microprocessor revenues and more rewarding improvements in performance and functions. Increasing battery capacity is still creeping along the roadmap. Until a small practical fuel cell becomes available, microprocessor developers must come up with power-reduction methods. According to MPR 2003, the instruction and data caches of ARM920T processor consume $44\%$ of total processor power. The rest of it is split into the power consumptions of the integer core, memory management units, bus interface unit and other essential CPU circuitry. And the relationships among CPU, peripherals and caches may change in the future. The processor working on higher operating frequency will exact larger cache RAM and consume more energy. In this paper, we propose advanced low power trace cache which caches traces of the dynamic instruction stream, and reduces cache access times. And we evaluate the performance of the trace cache and estimate the power of the trace cache, which is compared with conventional cache.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.58 no.7
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• pp.1443-1449
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• 2009

This paper presents a profiling model of a wide-window superscalar microprocessor using multiple branch prediction. The key idea is to apply statistical profiling technique to the superscalar microprocessor with a wide instruction window and a multiple branch predictor. The statistical profiling data are used to obtain a synthetical instruction trace, and the consecutive multiple branch prediction rates are utilized for running trace-driven simulation on the synthesized instruction trace. We describe our design and evaluate it with the SPEC 2000 integer benchmarks. Our performance model can achieve accuracy of 8.5 % on the average.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.9 no.2
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• pp.97-103
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• 2009

In this paper, the performance of a hybrid value predictor according to the instruction fetch rate on window size superscalar processors is evaluated. In general, the data dependency relations of instructions are increased with the number of the fetched instructions. Therefore, it is expected that the performance of a value predictor will be higher when the instruction fetch rate is increased. The performance is studied for the machine with collapsing buffer and he one with trace cache as an instruction fetch mechanism. As a result of experiment, it is showed that the performance effect of a value predictor is higher as the instruction fetch rate of instruction window size, IPC, predict rate on apply with non-tc and tc is increased.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.17 no.2
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• pp.251-256
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• 2017

Recently, multicore processor system is widely adopted not only in general purpose computers but also in embedded systems and mobile devices in order to improve performance. Since the power dissipation issue of multicore processor system is very significant, it must be estimated accurately in the early design stage. In this paper, a fast power analysis tool for a high performance multicore processor based on the trace-driven simulator has been developed. To achieve it, the power dissipation of each hardware unit per core are added. Using SPEC 2000 benchmarks as input, the trace-driven simulation has been performed to estimate the average power dissipation per instruction.

• Proceedings of the Korea Information Processing Society Conference
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• 2011.11a
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• pp.514-516
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• 2011

최근 지식 정보화 사회에 있어서 컴퓨터 네트워크 개방화와 함께 컴퓨터 시스템의 보안 위협이 급증하였다. 또한 기본적으로 데이터 보호에 초점을 맞추고 있기 때문에 접근에 대한 제한이 없으며 응용 프로그램에 따라 보안 운영방식이 다르다는 취약점을 가지고 있다. 본 논문은 하드웨어 기반 보안상태 모니터링 가시화를 위하여 TCG에서 제안한 TPM 칩을 기반으로 동작하는 컴퓨팅 환경의 신뢰 상태 및 시스템 자원에 대한 상태 정보를 실시간으로 모니터링하고 분기 추적 모니터링을 통해 논리적 에러의 초기위치를 파악하여 가시화한다.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.59 no.2
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• pp.423-428
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• 2010

In the initial design phase of superscalar microprocessors, a performance model is necessary. A theoretic performance model is very useful since performance for various architecture parameters can be obtained by simply computing equations, without repeating simulations, Previous studies established theoretic performance models using the relation between the instruction window size and the issue width, with the penalties due to branch mispredictions and cache misses. However, the study was intended for unlimited number of functional units, which is insufficient for the real case application. This paper proposes a superscalar microprocessor theoretical performance model which also works for the limited functional units. To enhance the accuracy of our limited functional unit model, instruction dependency rates are employed. By using trace-driven data of SPEC 2000 integer programs as input, this paper shows that the theoretically computed performance of superscalar microprocessor with limited number of functional units is quite similar to the measured performance.

• Journal of the Semiconductor & Display Technology
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• v.22 no.3
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• pp.78-83
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• 2023

This paper proposes a lightweight trace-driven Processing-In-Memory (PIM) simulator, TP-Sim. TP-Sim is a General Purpose PIM (GP-PIM) simulator that evaluates various PIM system performance-related metrics. Based on instruction and memory traces extracted from the Intel Pin tool, TP-Sim can replay trace files for multiple models of PIM architectures to compare its performance. To verify the availability of TP-Sim, we estimated three different system configurations on the STREAM benchmark. Compared to the traditional Host CPU-only systems with conventional memory hierarchy, simple GP-PIM architecture achieved better performance; even the Host CPU has the same number of in-order cores. For further study, we also extend TP-Sim as a part of a heterogeneous system simulator that contains CPU, GPGPU, and PIM as its primary and co-processors.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.16 no.5
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• pp.191-196
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• 2016

Recently, power dissipation is a very significant issue not only in embedded systems and mobile devices but also in high-end modern processors. Especially, by the prevalent use of smart phones and tablet PCs, low power consumption of microprocessors is requisite. In this paper, a fast power measurement tool for a high performance microprocessor based on the trace-driven simulator has been developed. The power model of the microprocessor consists of complex combinational circuits, array structures, and CAM structures. Using SPEC 2000 benchmarks as input, the trace-driven simulation has been performed to estimate the average power dissipation of each program.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.18 no.4
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• pp.169-175
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• 2018

Recently, power dissipation issue is very significant not only in high-end modern processors but also in embedded systems and mobile devices. Based on the power dissipation, hardware and software designers can correctly find the power/performance tradeoffs. Most power analysis tools calculate power dissipation when chip layout or floor planning are finished. In this paper, a trace-driven simulator that can interact with power analysis tool for an embedded microprocessor has been developed. Using MiBench embedded benchmarks as input, the trace-driven simulation has been performed to estimate the average power dissipation which is faster than the conventional tools.

• Journal of Korean Library and Information Science Society
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• v.3
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• pp.51-78
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• 1976

Since educating all students in learning how to learn and iic\il- to adapt thernselves to the changing society is the most desirable :.:.il:ii of education in the modern world, it is necessary that the library hc:one an increasingly important part of the students' learng activities. The development of the desire and necessary skills to seek mi! to acquire lino~vledge should be encouraged and planned by the acac:e:liic library. The effective instruction in the use of academic lihra1.1.- can provide the students with the cspxbility to carry on their own icL,i.!nal education through their life. This paper is to make a brief trace of the development of liGl-ary instruction in American universities and colleges oiyer the decades, providing the overview of many successful components of saxe representative projects and experiments, from which to clarify coi~in;on problems and principles involl-ed in them. Any one of standard approaches so far identified has turned o:lt to be not a perfect method in that each has its own merits and pl-oblcms. It may be that the process of analysis and evaluation is 1-aluab!e for better comprehensive perspectives in future program of the instr~iction in the use of academic libraries. An effort is sincerely made to giie an impetus to the recogrriiivn of the importance of library instruction in Korean academic .yorid to meet the urgent needs of the modern society.