• English Language & Literature Teaching
• /
• v.12 no.3
• /
• pp.267-286
• /
• 2006

The purpose of the study was to investigate what kinds of learning strategies EFL learners use to learn English grammar and what is benefit from structured grammar input processing. Students of the study consisted of 48 college students who took Practical English Grammar at a university in Kyung-Gi area and were divided into two groups based on grammar scores. The students were asked to take two grammar tasks and grammar tests and complete a survey including questions on grammar strategy and input processing. The results of the study are as follows. First, learners' grammar level has an effect on use of grammar attack strategy including asking teachers, using grammar books and given contexts whereas there was no significant difference between groups in the planning strategies, Among memory strategies, using grammar exercise and linking with already known structure demonstrated a significant difference between groups. Second, with regard to input processing, high level students got higher score on how much they understood the structured grammar input compared with low level students. Third, explicit implicit instruction added to input processing seems more comprehensible and more available than structured input only, Finally, it showed that there is positive relationship between perception and score of input processing tasks and grammar tests. Especially, learners' perception of input processing correlated more with final tests and tasks. Therefore, it suggests that the more input processing task need to develop and utilize in order to facilitate learners' intake.

• Proceedings of the Korea Information Processing Society Conference
• /
• 2014.11a
• /
• pp.53-56
• /
• 2014

Application specific instruction-set processor (ASIP) is a suitable design choice for system designers who seek both flexibility to handle various applications in the domain together with the performance. Successful development of an ASIP, however, requires a software development kit (SDK) to be provided along with the processor. Synopsys Processor Designer is an ASIP development tool, which takes as input a set of files written in a high-level architecture description language called LISA (Language for Instruction Set Architecture), and generates SDK as well as RTL. Recently, they have added support for the generation of LLVM compiler backend, though some manual work is required. In this paper, we introduce some details in porting LLVM compiler to a custom processor architecture in Synopsys Processor Designer.

• 제어로봇시스템학회:학술대회논문집
• /
• 1988.10a
• /
• pp.407-413
• /
• 1988

The architecture of a multiprocessor based programmable controller(MBPC) is presented. It consists of a host processor, processing elements, and Input/Output processors. Some problems in implementing such architecture are also described. To resolve them, we proposed and presented INFOBUS, a system bus for MBPC. The performances of INFOBUS and MBPC are analysed using both analytic models and simulations. Some results from the analysis will be given and validated. In case of 50% of BTI(Block Type Instruction) and 4 processors, the scanning time is shown to be 0.194msec/Kstep with some reasonable assumptions.

• Journal of the Korean Society for Library and Information Science
• /
• v.53 no.2
• /
• pp.5-27
• /
• 2019

The purpose of this study is to analyze the media of middle school social studies 1 textbooks with the information processing model and to suggest educational information services of teacher librarians under a collaborative Instruction. For this purpose, 1,089 inquiry tasks embedded in 8 types of textbooks for middle school social studies developed under the 2015 revised curriculum were analyzed. The media as an input element was analyzed by the type and the characteristic as a processing element was analyzed by the cognitive behavior types. And the aspect of the output factor of the media utilized the multiple intelligences. As a result of the analysis, the media in the inquiry task solving process mainly consisted of visual media based on photographs and illustrations and general reading materials. The processing method of media is understanding through analysis and inference through structuring. And the output utilized speaking and writing of the language intelligence. Based on the results, it is shown that educational information services that teacher librarians could provide for inquiry activities are composed of developing curriculum map, teaching inquiry processing and skills, and designing work sheets with graphic organizer and multiple intelligences under the information processing steps.

• Proceedings of the Korea Information Processing Society Conference
• /
• 2009.11a
• /
• pp.141-142
• /
• 2009

The PEFP (Proton Engineering Frontier Project) is constructing a 100MeV proton Linac (Linear Accelerator). The 20 MeV 20 mA proton beam has been serviced for an application in the fields of material, biological, information technology and medical sciences. For a stable and efficient acceleration of a proton beam, the control requirements must be optimized by studying various control methods. We propose that the integrated control system for the Linac machine components must be based on a distribution control method to improve a centralized control system. Based on EPICS (Experimental Physics and Industrial Control System) real-time software, the VME (Versa Module European package format) IOC (Input Output Controller) was developed under cross development environment with a RISC (Reduced Instruction Set Computer) PowerPC system. In this paper, we describe the design and implementation of distributed control system using the VME-based EPICS middleware for various components of the large proton accelerator.

• The Transactions of the Korean Institute of Electrical Engineers D
• /
• v.54 no.11
• /
• pp.643-649
• /
• 2005

A heart diagnosis system adopts Superconducting Quantum Interface Device(SQUD) sensors for precise MCG(MagnetoCardioGram) signal acquisitions. Such system needs to deal with hundreds of sensors, requiring fast signal sampling md precise analog-to-digital conversions(ADC). Our development of hardware board, processing 64-channel 12-bit in 1 ks/s speed, is built by using 8-channel ADC chips, 8-bit microprocessors, SPI interfaces, and specially designed parallel data transfers between microprocessors to meet the 1ks/s, i.e. 1 mili-second sampling interval. We extend the design into 256-channel hardware and analyze the speed .using the measured data from the 64-channel hardware. Since our design exploits full parallel processing, Assembly level coding, and NOP(No Operation) instruction for timing control, the design provides expandability and lowest system timing margin. Our result concludes that the data collection with 256-channel analog input signals can be done in 201.5us time-interval which is much shorter than the required 1 mili-second period.

• The Transactions of the Korea Information Processing Society
• /
• v.2 no.2
• /
• pp.264-276
• /
• 1995

In this paper, a technique for eliminating conditional branches in the compilers for superscalar processors is presented. The technique consists of three major steps. The first step transforms conditional branches into equivalent expressions using algebraic laws. The second step searches all possible instruction sequences for those expressions using GSO of Granlund/Kenner. Finally an optimal sequence that has the least dynamic count for the target superscalar processor is selected from the GSO output. Experiment result shows that for each conditional branch is the input program matched by one of the optimization patterns, the proposed technique outperforms more than 25% speedup of execution time over the original code when the GNU C compiler and the SuperSPARC processor are used.

• The KIPS Transactions:PartA
• /
• v.18A no.1
• /
• pp.1-10
• /
• 2011

Physical modeling has been widely used for sound synthesis since it synthesizes high quality sound which is similar to real-sound for musical instruments. However, physical modeling requires a lot of parameters to synthesize a large number of sounds simultaneously for the musical instrument, preventing its real-time processing. To solve this problem, this paper proposes a single instruction, multiple data (SIMD) based multi-core processor that supports real-time processing of sound synthesis of gayageum which is a representative Korean traditional musical instrument. The proposed SIMD-base multi-core processor consists of 12 processing elements (PE) to control 12 strings of gayageum in which each PE supports modeling of the corresponding string. The proposed SIMD-based multi-core processor can generate synthesized sounds of 12 strings simultaneously after receiving excitation signals and parameters of each string as an input. Experimental results using a sampling reate 44.1 kHz and 16 bits quantization show that synthesis sound using the proposed multi-core processor was very similar to the original sound. In addition, the proposed multi-core processor outperforms commercial processors(TI's TMS320C6416, ARM926EJ-S, ARM1020E) in terms of execution time ($5.6{\sim}11.4{\times}$ better) and energy efficiency (about $553{\sim}1,424{\times}$ better).

• The Journal of the Acoustical Society of Korea
• /
• v.29 no.3
• /
• pp.191-199
• /
• 2010

Physical modeling is a synthesis method of high quality sound which is similar to real sound for musical instruments. However, since physical modeling requires a lot of parameters to synthesize sound of a musical instrument, it prevents real-time processing for the musical instrument which supports a large number of sounds simultaneously. To solve this problem, this paper proposes a single instruction multiple data (SIMD) parallel processor that supports real-time processing of sound synthesis of guitar, a representative plucked string musical instrument. To control six strings of guitar, we used a SIMD parallel processor which consists of six processing elements (PEs). Each PE supports modeling of the corresponding string. The proposed SIMD processor can generate synthesized sounds of six strings simultaneously when a parallel synthesis algorithm receives excitation signals and parameters of each string as an input. Experimental results using a sampling rate 44.1 kHz and 16 bits quantization indicate that synthesis sounds using the proposed parallel processor were very similar to original sound. In addition, the proposed parallel processor outperforms commercial TI's TMS320C6416 in terms of execution time (8.9x better) and energy efficiency (39.8x better).

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.43 no.2 s.344
• /
• pp.51-59
• /
• 2006

Von Neumann architecture suffers from the interface between the central processing unit and the memory, which is called 'Von Neumann bottleneck' In this paper, we propose a scalable general-purpose associative processor (AP) based on content-addressable memory (CAM) which solves this problem and is suitable for the search-oriented applications. We propose an efficient instruction set and a structural scalability to extend for larger applications. We define twelve instructions and provide some reduced instructions to speed up which execute two instructions in a single instruction cycle. The proposed AP performs in a bit-serial, word-parallel fashion and can be considered as a 32-bit general-purpose parallel processor with a massively parallel SIMD structure. We design and simulate a maximum/minumum search greater-than/less-than search, and parallel addition to verify the proposed architecture. The algorithms are executed in a constant time O(k) regardless of the number of input data.