• Title/Summary/Keyword: input impedance matching

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Improved Impedance Matching of Dual-Frequency Microstrip Printed-Dipole Antenna with Conductor Back

  • Tangjitjesada, M.;Anantrasirichai, N.;Wakabayashi, T.
    • 제어로봇시스템학회:학술대회논문집
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    • 2003.10a
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    • pp.1668-1671
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    • 2003
  • A novel dual-frequency microstrip printed-dipole antenna operating at 5 GHz and 10 GHz is presented. This antenna is designed for wireless and mobile communication. The balance step coplanar strip is used to be a transmission line at the center of dipole with matching impedance at 50 ohm. Using the conductor strip align on the other side of antenna and adjust the width of step coplanar strip line to improved input impedance matching. By modification for matching impedance of dual frequency antenna are not affected to the radiation patterns. The Finite Difference Time Domain (FDTD) technique is applying to analyze the basic characteristic properties such as $S_{11}$ , input impedance , VSWR and radiation patterns. And these parameters are discussed. The analyze problem space are $51{\times}197{\times}175$ cells and cell dimension are ${\Delta}x=0.3\;mm$ and ${\Delta}y={\Delta}z=0.15\;mm$.

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NIC-Based Non-Foster Impedance Matching of a Resistively Loaded Vee Dipole Antenna (네거티브 임피던스 변환기에 기반을 둔 저항성 V 다이폴 안테나의 논 포스터 임피던스 매칭)

  • Yang, Hyemin;Kim, Kangwook
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.26 no.7
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    • pp.597-605
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    • 2015
  • Negative impedance converter(NIC)-based non-Foster impedance matching is proposed for an electrically small antenna. The antenna considered in this work is a resistively loaded vee dipole(RVD) antenna, which has considerable reflection at the feed point because of its large negative input reactance. The non-Foster matching circuit built near the feed point consists of two-stage NIC circuit and a capacitor connected between the stages. The NIC is realized by using operational amplifiers(op-amps) and resistors. The circuit is designed by considering of the input impedance according to the finite open-loop gain of the practical NICs. The stability test of the impedance-matched RVD antenna is performed. The non- Foster matching circuit is implemented with the RVD antenna. The measured impedance demonstrates that the proposed non-Foster matching circuit effectively reduces the input reactance of the RVD antenna.

Impedance Matching Method of an Inverted L Monopole Antenna (역 L 형 모노폴 안테나의 임피던스 정합방법)

  • Lim, Gye-jae
    • The Journal of Korea Institute of Information, Electronics, and Communication Technology
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    • v.6 no.1
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    • pp.18-22
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    • 2013
  • Input impedance of the inverted L antenna which is modified from a monopole antenna varies to very high input impedance value when the ratio of vertical height to horizontal length is reduced. So its impedance matching becomes very difficult. In this paper, we analyzed the input impedance variation range depending on the ratio of vertical height to horizontal length in the normal and ferrite thin film added configuration for the input impedance control. For the exact analysis involving the permittivity, permeability and conductivity of ferrite material, FDTD numerical method is used.

Impedance Tuning and Matching Characteristics of UHF RFID Tag for Increased Reading Range (인식거리 향상을 위한 UHF 대역 RFID 태그 임피던스 정합 설계)

  • Lee, Jong-Wook;Kwon, Hong-Il;Lee, Bom-Son
    • Proceedings of the Korea Electromagnetic Engineering Society Conference
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    • 2005.11a
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    • pp.279-284
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    • 2005
  • We investigated the impedance matching characteristics of UHF-band RFID tag antenna and tag chip for increased reading range. A voltage multiplier designed using 0.4 $\mu$m zero-$V_T$ MOSFET showed that DC output voltage of about 2 V can be obtained using standard CMOS process. The input impedance of the voltage multiplier was examined to achieve impedance matching to the RFID tag antenna using analytical and numerical approaches. The input impedance of the voltage multiplier could be varied in a wide range by selecting the size of MOSFET and the number of multiplying stages, and thus can be impedance matched to a tag antenna in presence of other tag circuit blocks. A meander line inductively-coupled RFID tag antenna operating at UHF band also shows the feasibility of impedance matching to tile RFID tag chip.

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Development of an Impedance Matching Layer in an Ultrasound Transducer with Gradient Properties

  • Jeong, Jihoon
    • Journal of Sensor Science and Technology
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    • v.27 no.6
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    • pp.374-379
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    • 2018
  • The piezocomposite transducer is widely used because it is highly efficient in transforming electric energy into mechanical energy, and its frequency range is broader than that of other types of ultrasound transducers. A general piezocomposite transducer is composed of an acoustic lens, impedance matching layers, piezoelectric materials, and backing layers. When an input voltage is applied to a piezoelectric material as an active material, it generates sound waves while vibrating. At that time, an impedance matching layer helps the sound waves to propagate forward while reducing the impedance mismatch that may occur at the interface between the active material and its front material. The impedance mismatch has a negative effect on the signal of an ultrasound transducer; thus, it is important to design a matching layer to overcome the issue. In this study, an optimized feature of a matching layer with gradient properties is studied. An objective function is defined to minimize both the average and the deviation of the reflection coefficients that are functions of the frequencies. As a result, an improvement in the signal characteristics with respect to the sensitivity and bandwidth is reported.

A New Approach for Built-in Self-Test of 4.5 to 5.5 GHz Low-Noise Amplifiers

  • Ryu, Jee-Youl;Noh, Seok-Ho
    • ETRI Journal
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    • v.28 no.3
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    • pp.355-363
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    • 2006
  • This paper presents a low-cost RF parameter estimation technique using a new RF built-in self-test (BIST) circuit and efficient DC measurement for 4.5 to 5.5 GHz low noise amplifiers (LNAs). The BIST circuit measures gain, noise figure, input impedance, and input return loss for an LNA. The BIST circuit is designed using $0.18\;{\mu}m$ SiGe technology. The test technique utilizes input impedance matching and output DC voltage measurements. The technique is simple and inexpensive.

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Input Impedance Matching Method of Inverted L Antenna using thin Ferrite Film (페라이트 薄膜을 이용한 逆L形 안테나의 入力임피던스 整合法)

  • Lim, Gye-Jae;Jung, Soo-Jin;Choi, Jong-Kwon
    • Resources Recycling
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    • v.13 no.6
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    • pp.26-30
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    • 2004
  • Input impedance of the inverted L antenna which is modified from a monopole antenna varies to very high input impedance value when the ratio of vertical height to horizontal length is reduced. So its impedance matching becomes very difficult. In this paper, we analyzed the input impedance variation range depending on the ratio of vertical height to horizontal length in the normal and ferrite thin film added configuration for the input impedance control. For the exact analysis involving the permittivity, permeability and conductivity of ferrite material, FDTD numerical method is used.

Input impedance matching method of inverted L antenna using thin ferrite film (페라이트 박막을 이용한 역 L 형 안테나의 입력임피던스 정합법)

  • Lim Gye Jae;Jung Soo Jin;Choi Jong Kwon
    • Proceedings of the Korean Institute of Resources Recycling Conference
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    • 2004.12a
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    • pp.43-51
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    • 2004
  • Input impedance of the inverted L antenna which is modified from a monopole antenna varies to very high input impedance value when the ration of vertical height to horizontal length is reduced. So its impedance matching becomes very difficult. In this paper, we analyzed the input impedance variation range depending on the ratio of vertical height to horizontal length in the normal and ferrite thin film added configuration for the input impedance control. For the exact analysis involving the permittivity, permeability and conductivity of ferrite material, FDTD numerical method is used.

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Design Analysis of Impedance Matching Circuit by Phasor Plot (페이저도에 의한 임피던스 정합회로 설계 해석)

  • Weon, La-Kyoung
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.26 no.11
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    • pp.1686-1696
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    • 2022
  • The impedance matching circuit design technique based on the phasor plot introduced in this paper is based on the impedance triangle of electric circuit. It is a technique that designs through the construction of a phasor figure using the values given to the matching circuit design. The design pattern is based on L-type, inverted L-type, T-type, and 𝜋-type, and unknown reactance elements are determined through phasor shapes. In this paper, using a design by phasor plot, we design several cases, such as the case where the input and output ports are pure resistance and have reactance. It was confirmed that the design value was verified by serial-parallel equivalent conversion to achieve matching. This design technique can immediately grasp the phase or size of input/output power, so it is expected to be applied mainly in a low frequency band due to rapid design change and application.

New Impedance Matching Scheme for 60 GHz Band Electro-Absorption Modulator Modules

  • Choi, Kwang-Seong;Chung, Yong-Duck;Kang, Young-Shik;Jun, Dong-Suk;Ahn, Byoung-Tae;Moon, Jong-Tae;Kim, Je-Ha
    • ETRI Journal
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    • v.28 no.3
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    • pp.393-396
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    • 2006
  • This letter proposes a new impedance matching scheme of a traveling wave electro-absorption modulator (TWEAM) module for a 60 GHz band radio-over-fiber (ROF) link. A microstrip band pass filter (BPF) was used to achieve impedance matching at the 60 GHz band, and termination resistance was carefully designed to obtain an input impedance close to $50\;{\Omega}$. Also, a bias circuit for the device was designed in the module. The measured return loss and frequency response show that the modulator module observes the characteristics of a filter without the need of a further tuning process.

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