• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.30 no.7C
• /
• pp.647-657
• /
• 2005

In this paper, we proposed a new lifting architecture for JPEG2000 and implemented to ASIC. We proposed a new cell to execute unit calculation of lifting using the property of lifting which is the repetitious arithmetic with same structure, and then recomposed the whole lifting by expanding it. After the operational sequence of lifting arithmetic was analyzed in detail and the causality was imposed for implementation to hardware, the unit cell was optimized. A new lifting kernel was organized by expanding simply the unit cell, and a lifting processor was implemented for Motion JPEG2000 using it. The implemented lifting kernel can accommodate the tile size of 1024$\times$1024, and support both lossy compression using the (9,7) filter and lossless compression using (5,3) filter. Also, it has the same output rate as input rate, and can continuously output the wavelet coefficients of 4 types(LL, LH, HL, HH) at the same time. The implemented lifting processor completed a course of ASIC using 0.35$\mu$m CMOS library of SAMSUNG. It occupied about 90,000 gates, and stably operated in about 150MHz though difference from the used macro cell for the multiplier. Finally, the improved operated in about 150MHz though difference from the used macro cell for the multiplier. Finally, the performance can be identified in comparison with the previous researches and commercial IPs.

• Aerospace Engineering and Technology
• /
• v.6 no.1
• /
• pp.83-91
• /
• 2007

An experimental verification of multipactor(MP) discharge for S-band diplexer as a sample DUT for space application by an in-house MP test facility is proposed. The designed diplexer having two BPFs for Rx and Tx is applied to a design of five pole inter-digital cavity type band pass filter with chebyshev response, it has 2.7 % bandwidth centered at 2.232 and 2.055 GHz for Rx, Tx, respectively. To avoid the MP discharge, the accurate design and analysis methods based on 3D EM field analysis are considered. The proposed in-house MP test facility consists of a phase detecting system using a doubly balanced mixer as a simple, low cost and real time MP test method compared with results of previously well-known MP detection systems as cross reference methods. The calculated MP threshold RF input power is 43.13 dBm. The measured one is 43 dBm and 44 dBm for CW, pulsed mode test, respectively.

• The Journal of the Acoustical Society of Korea
• /
• v.14 no.3
• /
• pp.49-60
• /
• 1995

This paper is a study on the design and implementation of the Korean Text-to-Speech system which is used for a small and simple system. In this paper, a parameter synthesis method is chosen for speech syntheiss method, we use PARCOR(PARtial autoCORrelation) coefficient which is one of the LPC analysis. And we use phoneme for synthesis unit which is the basic unit for speech synthesis. We use PARCOR, pitch, amplitude as synthesis parameter of voice, we use residual signal, PARCOR coefficients as synthesis parameter of unvoice. In this paper, we could obtain the 60% intelligibility by using the residual signal as excitation signal of unvoiced sound. The result of synthesis experiment, synthesis of a word unit is available. The controlling of phoneme duration is necessary for synthesizing of a sentence unit. For setting up the synthesis system, PC 486, a 70[Hz]-4.5[KHz] band pass filter for speech input/output, amplifier, and TMS320C30 DSP board was used.

• Journal of Astronomy and Space Sciences
• /
• v.20 no.4
• /
• pp.327-338
• /
• 2003

The aim of this paper is to describe the results of the study on the extreme-ultra-violet (EUV) solar telescope, which is designed to. a possible satellite mission. Since the EUV band can not be observed on the ground, the observation in EUV should be performed in space using a satellite or a rocket. Design of the Extreme-Ultra-Violet solar Telescope (BUVT) in this study is based on "Designing a small-sized engineering model of solar EUV telescope for a Korean satellite" (Han et al. 2001). Our EUVT design is satisfied with the requirements for a satellite in size and input voltage. The major goal of the study is to confirm if we can detect the specific wavelength (58.4nm to 62.9nm) with the EUVT. We describe re-designing of the EUVT to decrease a shelter ratio. Also we describe the technics in the optic system and the detector, which were used to manufacture the EUVT. We explain the detective program, which is to calculate the amount of the solar radiation, and the image data processing system.ng system.

• Journal of IKEEE
• /
• v.21 no.4
• /
• pp.331-337
• /
• 2017

In this paper, we present the design of a 20MHz bandwidth 3rd-order continuous-time low-pass sigma-delta modulator with low-noise and low-power consumption. The bandwidth of the system is sufficient to accommodate LTE and other wireless network standards. The 3rd-order low-pass filter with feed-forward architecture achieves the low-power consumption as well as the low complexity. The system uses 3bit flash quantizer to provide fast data conversion. The current-steering DAC achieves low-power and improved sensitivity without additional circuitries. Cross-coupled transistors are adopted to reduce the current glitches. The proposed system achieves a peak SNDR of 65.9dB with 20MHz bandwidth and power consumption of 32.65mW. The in-band IM3 is simulated to be 69dBc with 600mVp-p two tone input tones. The circuit is designed in a 0.18-um CMOS technology and is driven by 500MHz sampling rate signal.

• Asia-pacific Journal of Multimedia Services Convergent with Art, Humanities, and Sociology
• /
• v.7 no.3
• /
• pp.339-349
• /
• 2017

This paper proposes a four-stage algorithm for detecting lanes on a driving car. In the first stage, it extracts region of interests in an image. In the second stage, it employs a median filter to remove noise. In the third stage, a binary algorithm is used to classify two classes of backgrond and foreground of an input image. Finally, an image erosion algorithm is utilized to obtain clear lanes by removing noises and edges remained after the binary process. However, the proposed lane detection algorithm requires high computational time. To address this issue, this paper presents a parallel implementation of a real-time line detection algorithm on a multi-core architecture. In addition, we implement and simulate 8 different processing element (PE) architectures to select an optimal PE architecture for the target application. Experimental results indicate that 40×40 PE architecture show the best performance, energy efficiency and area efficiency.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.17 no.10 s.113
• /
• pp.967-975
• /
• 2006

In this paper, design and implementation of a very compact and cost effective front-end module are presented for IEEE 802.16 FWA(fixed Wireless Access) in the 40 GHz band. A multi-layer LTCC(Low Temperature Co-fred Ceramic) technology with cavity process to achieve excellent electrical performances is used to fabricate the front-end module. The wirebond matching circuit design of switch input/output port and waveguide transition to connect antenna are optimally designed to keep transmission loss low. To reduce the size of the front-end module, the dielectric waveguide filter is developed instead of the metal waveguide filter. The LTCC is composed of 6 layers(with the thickness of a layer of 100 um) having a relative dielectric constant of 7.1. The front-end module is implemented in a volume of $30{\times}7{\times}0.8mm^3$ and shows an overall insertion loss < 5.3 dB, and image rejection value > 49 dB.

• Journal of the Institute of Electronics Engineers of Korea SC
• /
• v.41 no.1
• /
• pp.41-54
• /
• 2004

In this paper, we propose a new digital hearing aid circuit that compensates the impaired threshold level changing nonlinearly using a multi-band compensation technique. In the algorithm the hearing frequency range 8kHz is divided into 64 bands which is 125Hz resolution. Each band is controlled finely to compensate the hearing impaired proportional to personal ROM table. The multi-band is introduced using a FFT/IFFT Processor which makes to control in frequency domain. As a result, the proposed circuit is more efficient $15\%$ than a conventional ones such as FIR filter architecture in terms of the compensation gun and accuracy. The hardware size was reduced $65\%$ than a general FFT by pre-handling of the input data.

• Journal of Electrical Engineering and Technology
• /
• v.12 no.1
• /
• pp.78-90
• /
• 2017

This paper presents the design of closed loop controllers operating a single-phase AC-DC three-level converter for improving power quality at AC mains. Closed loop inhibits outer voltage controller and inner current controller. Simulations of three level converter with three different voltage and current controller combinations such as PI-Hysteresis, Fuzzy-Hysteresis and Fuzzy tuned PI-Hysteresis are carried out in MATLAB/Simulink. Performance parameters such as input power factor and source current total harmonic distortion (THD) are considered for comparison of the three controller combinations. The fuzzy-tuned PI voltage controller with hysteresis current controller combination provides a better result, with a source-current THD of 0.93% and unity power factor without any source side filter for the three level converter. For load variations of 25% to 100%, a THD of less than 5% is obtained with a maximum value of only 1.67%. Finally, the fuzzy-tuned PI voltage with hysteresis controller combination is implemented in a Xilinx Spartan-6 XC6SLX25 FPGA board for experimental validation of power quality enhancement. A prototype 100 W, 0-24-48 V as output converter is considered for the testing of controller performance. A source-current THD of 1.351% is obtained in the experimental study with a power factor near unity. For load variations of 25% to 100%, the THD is found to be less than 5%, with a maximum value of only 2.698% in the experimental setup which matches with the simulation results.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.17 no.2 s.105
• /
• pp.171-177
• /
• 2006

A low-cost, high-performance 40 Gb/s clock recovery module using a phase-locked loop(PLL) for a 40 Gb/s optical receiver with the clock-hold function has been designed and implemented. It consists of a clock extractor circuit, an RF mixer and a frequency discriminator for phase/frequency detection, a VC-DRO, a phase shifter, and a clock-hold circuit. The extracted 40 GHz clock is synchronized with a stable 10 GHz VC-DRO. The clock stability and jitter characteristics of the implemented PLL-based clock recovery module are significantly improved as compared with those of the conventional open-loop type clock recovery module with a DR filter. The measured peak-to-peak RMS jitter is about 230 fs. When an input signal is dropped, the 40 GHz clock is maintained continuously by the hold circuit.