• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.13 no.12
• /
• pp.2662-2670
• /
• 2009

The effect of the reflector type for the SAW filter on the characteristics of the slanted finger IDT filter have been studied by computer simulation. The IDT was evaporated by Aluminum-Copper alloy. The design condition was optimized by the phase shift of the SAWfilter for WCDMA. We have employed that the number of pairs of the input and output IDT are 50 pairs and the thickness are $5,000{\AA}$, and the width and the space of reflector are $3.6{\mu}m$ and $2.0{\mu}m$, respectively. Frequency response of the fabricated SFIT filter has the property that the center frequency is about 190MHz and bandwidth at the 3dB is probably 8.2MHz. And we could obtain that the return loss is less then 16dB, the ripple characteristics is probably 4dB and the triple transit echo is less then 18dB after when we have matched impedance.

• Journal of Biomedical Engineering Research
• /
• v.25 no.2
• /
• pp.137-144
• /
• 2004

ECG signals are often contaminated with high-frequency noise such as muscle artifact, power line interference, and others. In the ECG signal processing, especially during a pre-processing stage, numerous noise removal techniques have been used to reduce these high-frequency noise without much distorting the original signal. This paper proposes a new type of digital filter with a continuously variable cutoff frequency to improve the signal quality This filter consists of a cutoff frequency controller (CFC) and variable cutoff frequency lowpass filter (VCF-LPF). From the noisy input ECG signal, CFC produces a cutoff frequency control signal using the signal slew rate. We implemented VCF-LPF based on two new filter design methods called convex combination filter (CCF) and weight interpolation fille. (WIF). These two methods allow us to change the cutoff frequency of a lowpass filter In an arbitrary fine step. VCF-LPF shows an excellent noise reduction capability for the entire time segment of ECG excluding the rising and falling edge of a very sharp QRS complex. We found VCF-LPF very useful and practical for better signal visualization and probably for better ECG interpretation. We expect this new digital filter will find its applications especially in a home health management system where the measured ECG signals are easily contaminated with high-frequency noises .

• Journal of the Institute of Electronics and Information Engineers
• /
• v.50 no.1
• /
• pp.157-165
• /
• 2013

In this paper, efficient digit-serial VLSI architecture for 1D (9,7) lifting-based discrete wavelet transform (DWT) filter has been proposed. The proposed architecture computes the DWT in digit basis, so that the required hardware is reduced. Also, the multiplication is replaced with the shift and add operation to minimize the hardware requirement. Bit allocation for input, output, and the internal data has been determined by analyzing the PSNR. We have carefully designed the data feedback latency not to degrade the performance in the recursive folded scheduling. The proposed digit-serial architecture requires small amount of hardware but achieve 100% of hardware utilization, so we try to optimize the tradeoffs between the hardware cost and the performance. The proposed architecture has been designed and verified by VerilogHDL and synthesized by Synopsys Design Compiler with a DongbuHitek $0.18{\mu}m$ STD cell library. The maximum operating frequency is 330MHz with 3,770 gates in equivalent two input NAND gates.

• Journal of Convergence for Information Technology
• /
• v.10 no.8
• /
• pp.47-52
• /
• 2020

In this study, a simulation investigation was conducted on the method of reducing switching noise and spurious emission among design methods for step-down DC-DC converter modules for automotive. A typical 4-layer converter circuit using a PMIC(Power Management Integrated Circuit) chip was presented, and the simulation results of conductive emissions at two input terminals (+, -) and the point between the input filter and the PMIC was performed in the 1.0~5.0MHz band and the 100MHz band. The results for the conducted and radiated emissions in the HF(3~30MHz) and VHF(30-300MHz) bands were presented. It showed an improvement of about 10dB over the bands by routing the output terminal placed on the 3 or 4-layer in the opposite direction to the input terminal. The result of this study is expected to be useful in the design of the DC-DC converter modules in the future because it gives a better improvement compared to the existing methods.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.17 no.1
• /
• pp.158-165
• /
• 2013

In this paper, a new circuit topology of an ultra-wideband (UWB) 3.1-10.6GHz CMOS low noise amplifier is presented. The proposed UWB low noise amplifier is designed utilizing RC feedback and LC filter networks which can provide good input impedance matching. In this design, the current-reused topology is adopted to reduce the power consumption and the inductor-peaking technique is applied for the purpose of bandwidth extension. The performance results of this UWB low noise amplifier simulated in $0.18-{\mu}m$ CMOS process technology exhibit a power gain of 14-14.9dB, an input matching of better than -10.8dB, gain flatness of 0.9dB, and a noise figure of 2.7-3.3dB in the frequency range of 3.1-10.6GHz. In addition, the input IP3 is -5dBm and the power consumption is 12.5mW.

• IEMEK Journal of Embedded Systems and Applications
• /
• v.15 no.5
• /
• pp.227-234
• /
• 2020

In this paper, we propose wav-U-Net to improve speech enhancement in heavy noisy environments, and it has implemented three principal techniques. First, as input data, we use 128 modified Mel-scale filter banks which can reduce computational burden instead of 512 frequency bins. Mel-scale aims to mimic the non-linear human ear perception of sound by being more discriminative at lower frequencies and less discriminative at higher frequencies. Therefore, Mel-scale is the suitable feature considering both performance and computing power because our proposed network focuses on speech signals. Second, we add a simple ResNet as pre-processing that helps our proposed network make estimated speech signals clear and suppress high-frequency noises. Finally, the proposed U-Net model shows significant performance regardless of the kinds of noise. Especially, despite using a single channel, we confirmed that it can well deal with non-stationary noises whose frequency properties are dynamically changed, and it is possible to estimate speech signals from noisy speech signals even in extremely noisy environments where noises are much lauder than speech (less than SNR 0dB). The performance on our proposed wav-U-Net was improved by about 200% on SDR and 460% on NSDR compared to the conventional Jansson's wav-U-Net. Also, it was confirmed that the processing time of out wav-U-Net with 128 modified Mel-scale filter banks was about 2.7 times faster than the common wav-U-Net with 512 frequency bins as input values.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.15 no.2
• /
• pp.134-139
• /
• 2004

A clock recovery circuit for a 40 Gb/s optical receiver has been designed and implemented. The clock recovery circuit consists of pre-amplifiers, a nonlinear circuit with diodes, a bandpass filter and a clock amplifier. Before implementing the 40 Gb/s clock recovery circuit, a 10 Gb/s clock recovery circuit has been successfully implemented and tested. With the 40 Gb/s clock recovery circuit, when a 40 Gb/s signal of -10 dBm was applied to the input of the circuit, the 40 GHz clock was recovered with the -20 dBm output power after passing through the nonlinear circuit. The output signal from the nonlinear circuit passes through a narrow-band filter, and then amplified. The implemented clock recovery circuit is planned to be used for the input of a phase locked loop to further stabilize the recovered clock signal and to reduce the clock jitter.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.44 no.8
• /
• pp.1-7
• /
• 2007

Class AB bipolar linear transconductors for high frequency applications ire proposed. They consist of a voltage follower, a resistor, and a current follower. The follower circuits are realized by translinear cells or unity-gain buffers. The proposed transconductors are simulated using an 8 GHz bipolar transistor-arrary parameter. Simulation results show that the transconductor using translinear cells has better linearity than one using unity-gain buffers whereas the latter has better temperature stability and higher input resistance than the former. In order to test their high frequency applicability, the transconductors are used to implement an 4th order IF bandpass filter.

• Journal of the Korean Institute of Telematics and Electronics T
• /
• v.35T no.3
• /
• pp.31-36
• /
• 1998

In this paper, Image Rejection Interdigital Filter(IRIF) for 5.8GHz wireless LAN was designed and implemented. When the input signal is -30dBm in the 4~8㎓ frequency band, the insertion loss including all kinds of loss is 6.3dB in the center frequency 5.775GHz. Therefore, it was showed practically insertion loss of about -3.3dB. Especially, image signal rejection is about -l7dB in the image frequency 6.475GHz. and skirt characteristics of the high frequency band is very excellent. Therefore, it was confirmed that the proposed IRIF is suitable for RF image signal rejection in the 5.8GHz wireless LAN system.

• The Journal of the Korea institute of electronic communication sciences
• /
• v.8 no.10
• /
• pp.1477-1483
• /
• 2013

This paper proposes a low-voltage current-mode integrator for a continuous-time current-mode baseband channel selection filter. The low-voltage current-mode linear cascode integrator is introduced to offer advantages of high current gain and improved unity-gain frequency. The proposed current-mode integrator has fully differential input and output structure consisting of CMOS complementary circuit. Additional cascode transistors which are operated in linear region are inserted for bias to achieve the low-voltage feature. Frequency range is also controllable by selecting proper bias voltage. From simulation results, it can be noticed that the implemented integrator achieves design specification such as low-voltage operation, current gain, and unity gain frequency.