• 제목/요약/키워드: initial delay time

검색결과 218건 처리시간 0.03초

In-Flight Alignment Algorithm Using Uplinked Radar Data Including Time Delay

  • Park, Chan-Ju;Kim, Heun-Beik;Song, Gi-Won
    • 제어로봇시스템학회:학술대회논문집
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    • 제어로봇시스템학회 2001년도 ICCAS
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    • pp.56.1-56
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    • 2001
  • Initial attitude error is one of the large error sources in the navigation errors of SDINS. And it is important to decide the initial attitude of SDINS. The method, like a self-alignment or a transfer alignment method, is required to a precise INS. If we do not have a precise INS, we should get large attitude error. After performing the initial alignment, a vehicle has the initial attitude error. Therefore, it results in navigation error due to the initial attitude error. But, if we use position information during flight, we could estimate and compensate a vehicle attitude error. So, we can maintain a precise attitude in spite of existing the initial attitude error. Using the uplinked position information from a land-based radar system, the new algorithm estimates the attitude of the SDINS during flight ...

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수소/공기/HFP 혼합기의 화학반응 및 점화지연 특성 (Characteristics of Chemical Reaction and Ignition Delay of $H_2$/Air/HFP Mixtures)

  • 이의주;오창보
    • 한국안전학회지
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    • 제25권1호
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    • pp.17-21
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    • 2010
  • The chemistry and ignition delay of hydrogen/air/HFP premixed mixtures was investigated numerically with unsteady perfectly stirred reactor(PSR). The detailed chemistry of 93 species and 817 reaction mechanism was introduced for hydrogen/air/HFP mixtures. The results shows the temporal concentration variations of major or reactants such as hydrogen and oxygen during autoignition were similar to the spatial distribution of premixed flame while water vapor produced at the ignition temperature was decomposed later, which can be clarified with the relate species production rates that the the re-growth (or shoulder) of OH concentration is a result of F radicals attacking $H_20$ forming OH and HF. For the stoichiometric $H_2$/air mixture inhibited by 20% HFP, HFP thermal decomposition reaction prevails over the radical attack such as H at initial stage. Even though relatively large HFP addition contributes to delay the ignition, chemical effect on the ignition delay is not effective because of late thermal decomposition of HFP. The most small ignition delay was observed at a slightly fuel lean condition ($\phi$ = 0.9), and temperature dependency of ignition delay was clearly shown near 900 K.

A Digital DLL with 4-Cycle Lock Time and 1/4 NAND-Delay Accuracy

  • Kim, Sung-Yong;Jin, Xuefan;Chun, Jung-Hoon;Kwon, Kee-Won
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제16권4호
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    • pp.387-394
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    • 2016
  • This paper presents a fully digital delay locked loop (DLL) that can acquire lock in four clock cycles with a resolution of a 1/4 NAND-delay. The proposed DLL with a multi-dither-free phase detector acquires the initial lock in four clock cycles with 1/2 NAND-delay. Then, it utilizes a multi-dither-free phase detector, a region accumulator, and phase blenders, to improve the resolution to a 1/4 NAND-delay. The region accumulator which continuously steers the control registers and the phase blender, adaptively controls the tracking bandwidth depending on the amount of jitter, and effectively suppresses the dithering jitter. Fabricated in a 65 nm CMOS process, the proposed DLL occupies $0.0432mm^2$, and consumes 3.7 mW from a 1.2-V supply at 2 GHz.

ISDN을 위한 최적 데이타 링크 흐름 제어에 관한 연구 (A Study on The Optimal Data Link Window Flow Control for ISDN)

  • 김동연;신우철;박민용;이상배
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 1987년도 전기.전자공학 학술대회 논문집(II)
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    • pp.1174-1177
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    • 1987
  • The design of flow control protocols for integrared networks with complete voice traffic on the data link level is investigated. The class of admissible flow control policies analyzed maximized the average data link throughput subject to an average system time delay constraints a finite intervals (O,s). In particular, it is shown that the optimum control law is bang-bang (window flow mechanism). The window size L can be analytically derived from maximum tolerated time delay T, the input arrival C of the queueing system, the duration of the time interval S, the initial number of packets in the queue.

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폐타이어 시편의 연소 특성 및 착화지연에 관한 실험적 연구 (An Experimental Study on Burning Time and Ignition Delay of Waste Tire Chips in High Temperature Environments)

  • 정종수;박은성;박종원
    • 대한기계학회논문집
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    • 제18권7호
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    • pp.1833-1839
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    • 1994
  • Experiments have been carried out to investigate the burning characteristics of waste tires in high temperature environments. The burning of waste tire chips consists of four stages ; evaporation of volatile matters, ignition, burning of volatile matters, and burning of solid carbon. Burning time of waste tire chips depends on the gas temperature and the initial weight of the chip. However, the environments. In the ceramic matrix burner with a ceramic radiation shield, the burning time of the waste tire chips becomes shorter than that without the shield. This is due to the increase in heat transfer to the tire chips by radiation.

SD를 이용한 공공 프로젝트의 지체요인 분석 (Delay Factor Analysis of Public Project Based on System Dynamics)

  • 이만형;이정민
    • 한국시스템다이내믹스연구
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    • 제4권2호
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    • pp.95-130
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    • 2003
  • The purpose of this study is to find what causes make public projects hold off, going beyond the planned deadline and budget. Using System Dynamics(SD) and their derivative Urban Dynamics(UD) models, it intends to analyze major feedback loops based on VENSIM and to simulate them with STELLA software, all of which are interrelated with various causes of project delay. To prevent or ameliorate project delay, first of all it advises to focus on endogenous delaying factors not exogenous ones. These factors either reinforce or balance certain loops in complex causal structure, In the case example on the Cremation Building Project in Cheongju, Residents’ participation demand make negotiation put off and delayed negotiation reinforces administrative-expediency planning in order to observe a time limit, on the other hand, once building consensus, it increase both the level of planning performance and public trust. In the meantime, the real planning process used to neglect residents opinions and manage public grievance only through compensation, he a result of simulation, visible fruit of negotiation in the initial phase seems to be not satisfactory owing to funds and time consumed, but after reaching an mutual agreement among stakeholders, planning performance is effective and strategic than administrative-expediency planning viewed in both financial and time angle. It proposes to devise specific tools schematizing project implementation. In order to upgrade the quality of project management, it recommends for planners to adopt key concepts based on SD/UD diagrams and causal loops, which would contribute to enriching Planning abbots.

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A 0.12GHz-1.4GHz DLL-based Clock Generator with a Multiplied 4-phase Clock Using a 0.18um CMOS Process

  • Chi, Hyung-Joon;Lee, Jae-Seung;Sim, Jae-Yoon;Park, Hong-June
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제6권4호
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    • pp.264-269
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    • 2006
  • A $0.12GHz{\sim}1.4GHz$ DLL-based clock generator with the capability of multiplied four phase clock generation was designed using a 0.18um CMOS process. An adaptive bandwidth DLL with a regulated supply delay line was used for a multiphase clock generation and a low jitter. An extra phase detector (PD) in a reference DLL solves the problem of the initial VCDL delay and achieves a fast lock time. Twice multiplied four phase clocks were generated at the outputs of four edge combiners, where the timing alignment was achieved using a coarse lock signal and the 10 multiphase clocks with T/8 time difference. Those four clocks were combined one more time using a static XOR circuit. Therefore the four times multiplication was achieved. With a 1.8V supply, the rms jitter of 2.1ps and the peak-to-peak jitter of 14.4ps were measured at 1.25GHz output. The operating range is $0.12GHz{\sim}1.4GHz$. It consumes 57mW and occupies 450*325um2 of die area.

EXISTENCE AND LONG-TIME BEHAVIOR OF SOLUTIONS TO NAVIER-STOKES-VOIGT EQUATIONS WITH INFINITE DELAY

  • Anh, Cung The;Thanh, Dang Thi Phuong
    • 대한수학회보
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    • 제55권2호
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    • pp.379-403
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    • 2018
  • In this paper we study the first initial boundary value problem for the 3D Navier-Stokes-Voigt equations with infinite delay. First, we prove the existence and uniqueness of weak solutions to the problem by combining the Galerkin method and the energy method. Then we prove the existence of a compact global attractor for the continuous semigroup associated to the problem. Finally, we study the existence and exponential stability of stationary solutions.

이벤트의 선택 확률을 고려한 시간 넷의 분석 알고리즘 및 응용 (A New Analytical Algorithm of Timed Net with Probabilities of Choices and Its Application)

  • 임재걸;주재훈
    • 한국경영과학회지
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    • 제30권4호
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    • pp.99-115
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    • 2005
  • For an analysis of the performance of a computer system, the minimum cycle time method has been widely used. The minimum cycle time method is a mathematical technique with which we can find the minimum duration time needed to fire all the transitions at least once and coming back to the Initial marking in a timed net. A timed net is a modified version of a Petri net where a transition is associated with a delay time. In the real world, an event is associated with a probability of occurrence. However, a timed net is not equipped with any facility of specifying probability of event occurrence. Therefore, the minimum cycle time method applied on a timed net can easily overlook probabilities of occurrences of events and yield a wrong result. We are proposing 'Timed Net with Probabilities of Choices' where a transition can be associated with both delay time and a probability of occurrence. We also introduce an algorithm for minimum cycle time analysis on a 'Timed Net with Probabilities of Choices'. As an example of application, we are performing an analysis of the location based service system using 'Timed Net with Probabilities of Choices'.

고전압 구형파 펄스 발생기에 관한 연구 (A study on High Voltage Squarewave Pulse Generator)

  • 김영배;유홍제;김종수
    • 전기학회논문지
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    • 제57권6호
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    • pp.1022-1025
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    • 2008
  • This paper presents the generation of the high voltage squarewave pulse using distributed RLC circuit. The demonstrated test was performed with the distributed RLC circuit which consists of the resistance, the inductance and the capacitance. Pspice simulation was also conducted about the experiment circuit. The result of the experiment was in good agreement with the result of the simulation. Theoretical analysis of the initial peak value at the squraewave pulse was derived from the results of the experiment and simulation. Additionally, the characteristics of the time delay was analyzed about the spherical gap switch and the surface discharge gap switch, respectively. It is concluded that the surface discharge gap switch is better than the spherical gap switch to reduce the time delay.