• Title/Summary/Keyword: information theory

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Color Media Instructions for Embedded Parallel Processors (임베디드 병렬 프로세서를 위한 칼라미디어 명령어 구현)

  • Kim, Cheol-Hong;Kim, Jong-Myon
    • Journal of KIISE:Computer Systems and Theory
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    • v.35 no.7
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    • pp.305-317
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    • 2008
  • As a mobile computing environment is rapidly changing, increasing user demand for multimedia-over-wireless capabilities on embedded processors places constraints on performance, power, and sire. In this regard, this paper proposes color media instructions (CMI) for single instruction, multiple data (SIMD) parallel processors to meet the computational requirements and cost goals. While existing multimedia extensions store and process 48-bit pixels in a 32-bit register, CMI, which considers that color components are perceptually less significant, supports parallel operations on two-packed compressed 16-bit YCbCr (6 bit Y and 5 bits Cb, Cr) data in a 32-bit datapath processor. This provides greater concurrency and efficiency for YCbCr data processing. Moreover, the ability to reduce data format size reduces system cost. The reduction in data bandwidth also simplifies system design. Experimental results on a representative SIMD parallel processor architecture show that CMI achieves an average speedup of 6.3x over the baseline SIMD parallel processor performance. This is in contrast to MMX (a representative Intel's multimedia extensions), which achieves an average speedup of only 3.7x over the same baseline SIMD architecture. CMI also outperforms MMX in both area efficiency (a 52% increase versus a 13% increase) and energy efficiency (a 50% increase versus an 11% increase). CMI improves the performance and efficiency with a mere 3% increase in the system area and a 5% increase in the system power, while MMX requires a 14% increase in the system area and a 16% increase in the system power.

Embedding Algorithm among Folded Hypercube, Even Network and Odd Network (폴디드 하이퍼큐브와 이븐연결망, 오드연결망 사이의 임베딩 알고리즘)

  • Kim, Jong-Seok;Sim, Hyun;Lee, Hyeong-Ok
    • Journal of KIISE:Computer Systems and Theory
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    • v.35 no.7
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    • pp.318-326
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    • 2008
  • In this paper, we will analyze embedding among Folded Hypercube, Even Network and Odd Network to further improve the network cost of Hypercube. We will show Folded Hypercube $FQ_n$ can be embedded into Even Network $E_{n-1}$ with dilation 2, congestion 1 and Even Network $E_d$ can be embedded into Folded Hypercube $FQ_{2d-3}$ with dilation 1. Also, we will prove Folded Hypercube $FQ_n$ can be embedded into Odd Network $O_{n-1}$ with dilation 2, congestion 1 and Odd Network $O_d$ can be embedded into Folded Hypercube $FQ_{2d-3}$ with dilation 2, congestion 1. Finally, we will show Even Network $E_d$ can be embedded into Odd Network $O_d$ with dilation 2, congestion 1 and Odd Network $O_d$ can be embedded into Folded Hypercube $E_{d-1}$ with dilation 2, congestion 1.

Design and Implementation of a File System that Considers the Space Efficiency of NVRAM (비휘발성 메모리의 공간적 효율성을 고려한 파일 시스템의 설계 및 구현)

  • Hyun Choul-Seung;Baek Seung-Jae;Choi Jong-Moo;Lee Dong-Hee;Noh Sam-H.
    • Journal of KIISE:Computer Systems and Theory
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    • v.33 no.9
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    • pp.615-625
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    • 2006
  • Nonvolatile memory technology is evolving continuously and commercial products such as FeRAM and PRAM are now challenging their markets. As NVRAM has properties of both memory and storage, it can store persistent data objects while allowing fast and random access. To utilize NVRAM for general purpose storing of frequently updated data across power disruptions, some essential features of the file system including naming, recovery, and space management are required while exploiting memory-like properties of NVRAM. Conventional file systems, including even recently developed NVRAM file systems, show very low space efficiency wasting more than 50% of the total space in some cases. To efficiently utilize the relatively expensive NVRAM, we design and implement a new extent-based space-thrifty file system, which we call NEBFS (NVRAM Extent-Based File System). We analyze and compare the space utilization of conventional file systems with NEBFS and validate the results with experimental results observed from running the file system implementations on a system with actual NVRAM installed as well as on systems emulating NVRAM. We show that NEBFS has high space efficiency compared to conventional file systems.

Hardware-Software Cosynthesis of Multitask Multicore SoC with Real-Time Constraints (실시간 제약조건을 갖는 다중태스크 다중코어 SoC의 하드웨어-소프트웨어 통합합성)

  • Lee Choon-Seung;Ha Soon-Hoi
    • Journal of KIISE:Computer Systems and Theory
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    • v.33 no.9
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    • pp.592-607
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    • 2006
  • This paper proposes a technique to select processors and hardware IPs and to map the tasks into the selected processing elements, aming to achieve high performance with minimal system cost when multitask applications with real-time constraints are run on a multicore SoC. Such technique is called to 'Hardware-Software Cosynthesis Technique'. A cosynthesis technique was already presented in our early work [1] where we divide the complex cosynthesis problem into three subproblems and conquer each subproblem separately: selection of appropriate processing components, mapping and scheduling of function blocks to the selected processing component, and schedulability analysis. Despite good features, our previous technique has a serious limitation that a task monopolizes the entire system resource to get the minimum schedule length. But in general we may obtain higher performance in multitask multicore system if independent multiple tasks are running concurrently on different processor cores. In this paper, we present two mapping techniques, task mapping avoidance technique(TMA) and task mapping pinning technique(TMP), which are applicable for general cases with diverse operating policies in a multicore environment. We could obtain significant performance improvement for a multimedia real-time application, multi-channel Digital Video Recorder system and for randomly generated multitask graphs obtained from the related works.

Bus Splitting Techniques for MPSoC to Reduce Bus Energy (MPSoC 플랫폼의 버스 에너지 절감을 위한 버스 분할 기법)

  • Chung Chun-Mok;Kim Jin-Hyo;Kim Ji-Hong
    • Journal of KIISE:Computer Systems and Theory
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    • v.33 no.9
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    • pp.699-708
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    • 2006
  • Bus splitting technique reduces bus energy by placing modules with frequent communications closely and using necessary bus segments in communications. But, previous bus splitting techniques can not be used in MPSoC platform, because it uses cache coherency protocol and all processors should be able to see the bus transactions. In this paper, we propose a bus splitting technique for MPSoC platform to reduce bus energy. The proposed technique divides a bus into several bus segments, some for private memory and others for shared memory. So, it minimizes the bus energy consumed in private memory accesses without producing cache coherency problem. We also propose a task allocation technique considering cache coherency protocol. It allocates tasks into processors according to the numbers of bus transactions and cache coherence protocol, and reduces the bus energy consumption during shared memory references. The experimental results from simulations say the bus splitting technique reduces maximal 83% of the bus energy consumption by private memory accesses. Also they show the task allocation technique reduces maximal 30% of bus energy consumed in shared memory references. We can expect the bus splitting technique and the task allocation technique can be used in multiprocessor platforms to reduce bus energy without interference with cache coherency protocol.

Design of Software and Hardware Modules for a TCP/IP Offload Engine with Separated Transmission and Reception Paths (송수신 분리형 TCP/IP Offload Engine을 위한 소프트웨어 및 하드웨어 모듈의 설계)

  • Jang Hank-Kok;Chung Sang-Hwa;Choi Young-In
    • Journal of KIISE:Computer Systems and Theory
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    • v.33 no.9
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    • pp.691-698
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    • 2006
  • TCP/IP Offload Engine (TOE) is a technology that processes TCP/IP on a network adapter instead of a host CPU to reduce protocol processing overhead from the host CPU. There have been some approaches to implementing TOE: software TOE based on an embedded processor; hardware TOE based on ASIC implementation; and hybrid TOE in which software and hardware functions are combined. In this paper, we designed software modules and hardware modules for a hybrid TOE on an FPGA that had two processor cores. Software modules are based on the embedded Linux. Hardware modules are for data transmission (TX) and reception (RX). One core controls the TX path and the other controls the RX path of the Linux. This TX/RX path separation mechanism can reduce task switching overheads between processes and overcome poor performance of single embedded processor. Hardware modules deal with creating headers for outgoing packets, processing headers of incoming packets, and fetching or storing data from or to the host memory by DMA. These can make it possible to improve the performance of data transmission and reception. We proved performance of the TOE with separated transmission and reception paths by performing experiments with a TOE network adapter that was equipped with the FPGA having processor cores.

Two-Stage Evolutionary Algorithm for Path-Controllable Virtual Creatures (경로 제어가 가능한 가상생명체를 위한 2단계 진화 알고리즘)

  • Shim Yoon-Sik;Kim Chang-Hun
    • Journal of KIISE:Computer Systems and Theory
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    • v.32 no.11_12
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    • pp.682-691
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    • 2005
  • We present a two-step evolution system that produces controllable virtual creatures in physically simulated 3D environment. Previous evolutionary methods for virtual creatures did not allow any user intervention during evolution process, because they generated a creature's shape, locomotion, and high-level behaviors such as target-following and obstacle avoidance simultaneously by one-time evolution process. In this work, we divide a single system into manageable two sub-systems, and this more likely allowsuser interaction. In the first stage, a body structure and low-level motor controllers of a creature for straight movement are generated by an evolutionary algorithm. Next, a high-level control to follow a given path is achieved by a neural network. The connection weights of the neural network are optimized by a genetic algorithm. The evolved controller could follow any given path fairly well. Moreover, users can choose or abort creatures according to their taste before the entire evolution process is finished. This paper also presents a new sinusoidal controller and a simplified hydrodynamics model for a capped-cylinder, which is the basic body primitive of a creature.

Equivalent Friction Angle and Cohesion of the Generalized Hoek-Brown Failure Criterion in terms of Stress Invariants (응력불변량으로 표현한 일반화된 Hoek-Brown 파괴조건식의 등가 마찰각 및 점착력)

  • Lee, Youn-Kyou;Choi, Byung-Hee
    • Tunnel and Underground Space
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    • v.22 no.6
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    • pp.462-470
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    • 2012
  • Implementing the generalized Hoek-Brown failure criterion in the framework of the Mohr-Coulomb criterion requires the calculation of the equivalent friction angle and cohesion. In the conventional method based on the Balmer (1952)'s theory, the tangential instantaneous friction angle and cohesion are expressed in terms of the minimum principal stress ${\sigma}_3$, which does not provide the information about the dependency of the equivalent parameters on the hydrostatic pressure and the stress path. In this study, this defect of the conventional method has been overcome by representing the equivalent parameters in terms of stress invariants. Through the example implementation of the new method, the influence of the magnitude of the hydrostatic pressure and the Lode angle on the tangential instantaneous friction angle and cohesion is investigated. It turns out that the tangential instantaneous friction angle is maximum when the stress condition is triaxial extension, while the tangential cohesion is maximum when the stress condition is triaxial compression. The dependency of the equivalent Mohr-Coulomb strength parameters on the hydrostatic pressure and the Lode angle tends to be more substantial for the favorable rockmass of larger GSI value.

Performance of Serial Communication Protocols through Conducting Threads (전도성사를 매체로 한 직렬 통신 프로토콜 성능)

  • Kim, Na-Young;Kim, Hwan;Kim, Juk-Young;Kwon, Young-Mi
    • Journal of Internet Computing and Services
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    • v.12 no.5
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    • pp.21-28
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    • 2011
  • Recently medical and entertainment applications using conducting textile are suggested, but the data of conducting threads are not characterized, classified and verified. Only the data sheet published by manufacturing companies is available. Thus we need to verify the performances of the threading threads in communication. And we need a guideline if the existing communication protocols can be used for the conducting threads communication or the new specific communication protocols have to be developed for the communication. This paper classifies the characteristics of conducting threads made by domestic and overseas companies. Based on the criteria we classified conducting threads into three classes: class A, class B and class C. Further we carried out experiments to verify the adaptability of existing simple serial communication protocols such as RS232. Six different conducting threads are used in experiments and the length of each thread was 0.5m, 1m, 2m and 3m. The data transmission rate and error rate are collected and analyzed. RS485 is very prone to error due to static electricity from human and environment. So it may not be appropriate as long-distance communication protocol up to 12km which is possible in theory. RS232 shows stable and error-less data transmission ability even though every conducting thread didn’t show transmission capability over RS232. USB protocol shows high data rate transmission but the distance cannot be exceeded over 2m. Additionally, USB requires stable power supply. But if the power is supplied through conducting thread, its function is not.

Pressure Distribution over Tube Surfaces of Tube Bundle Subjected to Two-Phase Cross-Flow (이상 유동에 놓인 관군의 표면에 작용하는 압력 분포)

  • Sim, Woo Gun
    • Transactions of the Korean Society of Mechanical Engineers B
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    • v.37 no.1
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    • pp.9-18
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    • 2013
  • Two-phase vapor-liquid flows exist in many shell and tube heat exchangers such as condensers, evaporators, and nuclear steam generators. To understand the fluid dynamic forces acting on a structure subjected to a two-phase flow, it is essential to obtain detailed information about the characteristics of a two-phase flow. The characteristics of a two-phase flow and the flow parameters were introduced, and then, an experiment was performed to evaluate the pressure loss in the tube bundles and the fluid-dynamic force acting on the cylinder owing to the pressure distribution. A two-phase flow was pre-mixed at the entrance of the test section, and the experiments were undertaken using a normal triangular array of cylinders subjected to a two-phase cross-flow. The pressure loss along the flow direction in the tube bundles was measured to calculate the two-phase friction multiplier, and the multiplier was compared with the analytical value. Furthermore, the circular distributions of the pressure on the cylinders were measured. Based on the distribution and the fundamental theory of two-phase flow, the effects of the void fraction and mass flux per unit area on the pressure coefficient and the drag coefficient were evaluated. The drag coefficient was calculated by integrating the measured pressure on the tube by a numerical method. It was found that for low mass fluxes, the measured two-phase friction multipliers agree well with the analytical results, and good agreement for the effect of the void fraction on the drag coefficients, as calculated by the measured pressure distributions, is shown qualitatively, as compared to the existing experimental results.