• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.6
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• pp.44-50
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• 2002

A novel technique for minimization of simultaneous switching noise is Presented. Dual Layer Power Line (DLPL) structure i:; newly proposed for a possible silicon realization of a mutual inductor, with which an instant large current in the power line is half-divided flowing through two different, but closely coupled, layers in opposite directions. This mutual inductance between two power layers enables us to significantly reduce the switching noise. SPICE simulations show that with a mutual coupling coefficient higher than 0.8, the switching noise reduces by 63% compared to the previously reported solutions. This DLPL technique can also be applied to PCB artworks.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.19 no.8
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• pp.837-843
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• 2008

This paper proposes a power divider based on meta-material structure with dual-band operation. The meta-material structures of left-hand characteristic are constituted of series capacitors and shunt inductors, but they have parasitic series inductance and shunt capacitance effects. There is represented the composite right/ left-handed transmission line (CRLH-TL) model. When the power divider is implemented by using the CRLH-TL, the power divider can operate dual band. To verify the power divider with dual band, we are implemented to operate dual-band that is 0.88 GHz and 1.67 GHz. The characteristics of divider have the return loss less than each 21.0 dB and 15.8 dB and the insertion loss better than 3.83 dB and 3.64 dB at each frequency. Also, the output phase difference is $3{\sim}6^{\circ}$.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.20 no.11
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• pp.1130-1137
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• 2009

This paper proposes a new clock routing design for suppressing clock harmonic effects in a Printed Circuit Board (PCB) for a terrestrial Digital Multimedia Broadcasting(DMB) system. Typical crystal reference frequencies that are widely used in DMB tuners are 16.384 MHz, 19.2 MHz, 24.576 MHz. When the high-order harmonic components of these reference frequencies fall near the RF channel frequencies, receiver sensitivity of the tuners is seriously degraded. In this work, we propose a new clock routing design in order to address the clock harmonic coupling issue. The proposed design incorporates two inductors for isolating the clock ground from the main ground, and adopts a new strip line-style routing instead of the conventional microstrip line style routing to minimize the overlap area with the main ground. As a result, the RF sensitivity of the T-DMB tuner is improved by 2 dB.

• Proceedings of the KIEE Conference
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• 2002.07c
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• pp.1524-1526
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• 2002

본 논문에서는 $1.62{\times}1.0{\times}0.88mm^3$ 크기의 C-type과 $1.58{\times}0.82{\times}0.94mm^3$ 크기의 H-type RF 칩 인덕터를 제작하고 그들의 고주파 특성을 비교하였다. 본 연구에서는 저손실 $Al_2O_3$ 코아 물질과 직경 $40{\mu}m$의 구리(Cu) 코일을 사용하였다. 권선수를 $2{\sim}14$회로 하여 인덕턴스(L), 품질계수(Q), 임피던스의 크기와 위상, 커패시턴스(C)를 HP4291B Impedance/Material Analyzer로 측정하였다. 10회 권선시 C-type은 55nH, H-type은 67nH, 14회 권선시 C-type은 100nH, H-type은 122nH 정도로 측정되었다. 실험 결과 H-type이 C-type보다 동일 권선수에 대하여 높은 인덕턴스와 높은 자기공진주파수(SRF)를 나타냄을 확인하였다. 또한 최대 품질계수는 두 형태가 거의 비슷한 값($55{\sim}87$)을 가짐을 관찰하였다. 따라서 H-type이 C-type보다 우수한 성질을 나타냄을 알 수 있다.

• Journal of Welding and Joining
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• v.17 no.1
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• pp.133-144
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• 1999

To fine seam annealer capacity of through thickness seam annealing in terms of through thickness microstructure change with increased toughness and elongation leaving heat trace on it, high strength steel pipes of ERW with different thickness were tested in different seam annealing temperature measured on the outer surface of pipes. Annealing temperature and microstructure of the weld seam were changed through applied seam annealing condition. Toughness and tensile test with hardness and microstructure analysis were done on the annealed weld seam to fine its characteristics as a primary step and annealing characteristics according to different seam annealing condition. Through a study of annealed ERW weld seam characteristics and seam annealing technology, amount of electric power should apply in decreased manner to arranged inductors of annealer in the order of 1st, 2nd, 3rd, so on for proper seam annealing. For example of 15.4mm thick and 610mm outside diameter pipe, applied power for proper seam annealing is 600 -650kw at 1st inductor, 450 - 500kw at 2nd inductor, 200-250 kw at 3rd inductor of annealer during 10 - 12M/minute moving speed of pipe. Also, the penetration depth of heat trace along the thickness direction of weld during seam annealing can be estimated through the equation 17mm/kv$\times$voltage(kv) with the microstructure and hardness analysis of thick weld seam as well as study of seam annealing and comparison of cooling condition to CCT diagram of low carbon high strength steel. From this result, the difference between the technological applicability of full annealing condition based on phase diagram and full penetration of heat trace based on CCT diagram along the thickness of weld seam is discussed.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.16 no.2
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• pp.9-17
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• 2002

A high-efficiency electronic ballast for HID lamps is presented. The ballast consists of a PFC and a resonant inverter. To reduce losses of the ballast, DC link voltage should be determined by taking into account the peak voltage of lamp and the maximum flux density should be kept 0.2[T] on all of inductors. AR inductor at bridge diode is employed in order to remove currant harmonics from PFC. An inductor is connected in series with an electrolytic capacitor at DC link to reject high-frequency current. The acoustic resonance is eliminated using the stead spectrum technique. The electronic ballast for 250[W] metal-halide discharge lamp is implemented and 96[%] efficiency, no acoustic resonance and low conducted EMI level are accomplished.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.15 no.2
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• pp.165-171
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• 2004

In this paper, the modeling and design of high-Q multilayer passives have been investigated, and multilayer diplexer for GSM/DCS applications has been designed and fabricated using the passives. Modeling of a multilayer inductor was performed by the subsystems of distributed components, and using the modeling the optimal structures of the high-Q multilayer inductor could be designed by analyzing parasitics and couplings which affect their frequency characteristics. Multilayer diplexers for GSM/DCS applications have been designed and fabricated using LTCC technology. LPF for GSM band had the passband insertion loss of less than 0.55 dB, the return loss of more than 12 dB, and the isolation level of more than 26 dB. HPF for DCS band had the passband insertion loss of less than 0.82 dB, the return loss of more than 11 dB, and the isolation level of more than 38 dB.

• Journal of the Korean Magnetics Society
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• v.11 no.5
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• pp.222-225
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• 2001

The planar type inductors have a good potential for the application of miniaturized low power DC-DC converters. For those high quality application, the reduction of coil loss and also magnetic films which have good high frequency properties are required. Fabricated inductor was consisted of FeTaN/Ti magnetic film and electroplated Cu coil thickness of 100$\mu\textrm{m}$ and $SiO_2$ as a insulating layer. The inductor was designed double rectangular spiral shape for magnetic field highly confining within the device. The measured value of inductance and resistance were 980 nH and 1.7 $\Omega$ at 1 MHz as operating frequency of device. The Q factor is 3.55 at 1 MHz.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.44 no.1
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• pp.69-78
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• 2007

A Frequency synthesizer for T-DMB and mobile-DTV applications was designed using $0.18{\mu}m$ CMOS process with 1.8V supply. PMOS transistors were chosen for VCO core to reduce phase noise. The VCO range is 920MHz-2100MHz using switchable inductors, capacitors and varactors. Varactor biases that improve varactor acitance characteristics were minimized as two, and $K_{VCO}$(VCO gain) value was aintained by switchable varactor. Additionally, VCO was designed that VCO gain and the interval of VCO gain were maintained using VCO gain compensation logic. VCO, PFD, CP and LF were verified by Cadence Spectre, and divider was simulated using Matlab Simulink, ModelSim and HSPICE. VCO consumes 10mW power, and is 56.3% tuning range. VCO phase noise is -127dBc/Hz at 1MHz offset for 1.58GHz output frequency. Total power consumption of the frequency synthesizer is 18mW, and lock time is about $140{\mu}s$.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.5
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• pp.128-133
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• 2013

In this paper, octagonal inductors for RFIC designs was fabricated with 90nm CMOS Technology to compare its quality factor and the effective inductance as functions of radius and number of turn. The quality factor decreases as the inner radius and the number of metal turned increase. However, the effective inductance increases with the increasing the inner radius and the number of metal turned. Therefore, the inductor structure should be decided according to the relative importance of Q-factor and inductance.