• The Korean Journal of Physiology and Pharmacology
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• 제12권2호
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• pp.59-64
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• 2008

In our previous study, we found that spermine and putrescine inhibited spontaneous and acetylcholine (ACh)-induced contractions of guinea-pig stomach via inhibition of L-type voltage- dependent calcium current ($VDCC_L$). In this study, we also studied the effect of spermidine on mechanical contractions and calcium channel current ($I_{Ba}$), and then compared its effects to those by spermine and putrescine. Spermidine inhibited spontaneous contraction of the gastric smooth muscle in a concentration-dependent manner ($IC_{50}=1.1{\pm}0.11mM$). Relationship between inhibition of contraction and calcium current by spermidine was studied using 50 mM high $K^+$-induced contraction: Spermidine (5 mM) significantly reduced high $K^+$ (50 mM)-induced contraction to 37${\pm}$4.7% of the control (p<0.05), and inhibitory effect of spermidine on $I_{Ba}$ was also observed at a wide range of test potential in current/voltage (I/V) relationship. Pre- and post-application of spermidine (5 mM) also significantly inhibited carbachol (CCh) and ACh-induced initial and phasic contractions. Finally, caffeine (10 mM)-induced contraction which is activated by $Ca^{2+}$-induced $Ca^{2+}$ release (CICR), was also inhibited by pretreatment of spermidine (5 mM). These findings suggest that spermidine inhibits spontaneous and CCh-induced contraction via inhibition of $VDCC_L$ and $Ca^{2+}$ releasing mechanism in guinea-pig stomach.

• 한국정보통신학회논문지
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• 제17권1호
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• pp.145-150
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• 2013

본 연구에서는 차세대 나노소자인 DGMOSFET에 대하여 문턱전압 이하영역에서 발생하는 단채널 효과 중 문턱전압 및 드레인유도장벽감소의 변화를 스켈링 이론에 따라 분석하였다. 포아송방정식의 분석학적 해를 구하기 위하여 전하분포함수에 대하여 가우시안 함수를 사용함으로써 보다 실험값에 가깝게 해석하였으며 이때 가우시안 함수의 변수인 이온주입범위 및 분포편차 그리고 소자 파라미터인 채널의 두께, 도핑농도 등에 대하여 문턱전압 특성의 변화를 관찰하였다. 본 연구의 모델에 대한 타당성은 이미 기존에 발표된 논문에서 입증하였으며 본 연구에서는 이 모델을 이용하여 문턱전압이하 특성을 분석하였다. 분석결과 스켈링 이론 적용 시 문턱전압 및 드레인유도장벽감소 현상이 변화하였으며 변화 정도는 소자파라미터에 따라 변화한다는 것을 관찰하였다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2002년도 하계학술대회 논문집 A
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• pp.130-132
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• 2002

Because of the continuous growth of energy consumption and also the tendency to site power lines and pipelines along the same route, the close proximity of power lines and buried metallic pipelines has become more and more frequent. Therefore there has been and still is a slowing concern about possible hazards resulting from the influence of power lines on metallic pipelines. Underground pipelines that run parallel to or in close proximity to power lines are subjected to induced voltages caused by the time-varying magnetic fields produced by the power line currents. The induced electro- motive force cause currents circulation in the pipeline and voltages between the pipeline and surrounding earth. This paper analyzes the induced voltage on the gas pipelines buried in parallel with 22.9kV distribution lines. Their magnitude depends on the length of parallelism and on the distance between distribution lines and pipeline.

• JSTS:Journal of Semiconductor Technology and Science
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• 제3권4호
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• pp.217-222
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• 2003

A new two-dimensional analytical model for the potential distribution and drain-induced barrier lowering (DIBL) effect of fully depleted short-channel Silicon-on-insulator (SOI)-MESFET's has been presented in this paper. The two dimensional potential distribution functions in the active layer of the device is approximated as a simple parabolic function and the two-dimensional Poisson's equation has been solved with suitable boundary conditions to obtain the bottom potential at the Si/oxide layer interface. It is observed that for the SOI-MESFET's, as the gate-length is decreased below a certain limit, the bottom potential is increased and thus the channel barrier between the drain and source is reduced. The similar effect may also be observed by increasing the drain-source voltage if the device is operated in the near threshold or sub-threshold region. This is an electrostatic effect known as the drain-induced barrier lowering (DIBL) in the short-gate SOI-MESFET's. The model has been verified by comparing the results with that of the simulated one obtained by solving the 2-D Poisson's equation numerically by using the pde toolbox of the widely used software MATLAB.

• The Korean Journal of Physiology and Pharmacology
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• 제8권2호
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• pp.101-110
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• 2004

Voltage-sensitive release mechanism was pharmacologically dissected from the $Ca^{2+}-induced\;Ca^{2+}\;release$ in the SR $Ca^{2+}$ release in the rat ventricular myocytes patch-clamped in a whole-cell mode. SR $Ca^{2+}$ release process was monitored by using forward-mode $Na^+-Ca^{2+}$ exchange after restriction of the interactions between $Ca^{2+}$ from SR and $Na^+-Ca^{2+}$ exchange within micro-domains with heavy cytosolic $Ca^{2+}$ buffering with 10 mM BAPTA. During stimulation every 10 s with a pulse roughly mimicking action potential, the initial outward current gradually turned into a huge inward current of $-12.9{\pm}0.5\;pA/pF$. From the inward current, two different inward $I_{NCX}s$ were identified. One was $10\;{\mu}M$ ryanodine-sensitive, constituting $14.2{\pm}2.3%$. It was completely blocked by $CdCl_2$ (0.1 mM and 0.5 mM) and by $Na^+-depletion$. The other was identified by 5 mM $NiCl_2$ after suppression of $I_{CaL}$ and ryanodine receptor, constituting $14.8{\pm}1.6%$. This latter was blocked by either 10 mM caffeine-induced SR $Ca^{2+}-depletion$ or 1 mM tetracaine. IV-relationships illustrated that the latter was activated until the peak in $30{\sim}35\;mV$ lower voltages than the former. Overall, it was concluded that the SR $Ca^{2+}$ release process in the rat ventricular myocytes is mediated by the voltage-sensitive release mechanism in addition to the $Ca^{2+}-induced-Ca^{2+}\;release$.

• 한국전자파학회논문지
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• 제9권6호
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• pp.802-812
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• 1998

고전압 발/ 변전소의 근무자나 송전선 작업자 및 주변거주자가 전계 노출에 안전해야 함은 중요한 일이다. 본 논문에서는 복잡하고 계산시간이 많이 소요되는 인체의 3차원 유도전류를 계산하기 위해 전압원(송전선 로)의 효과적인 모델링 기법을 사용하여 전압원과 피유도체를 분리하지 않고 직접 3차원 정전용량을 구함으 로써 불평등 전계하의 임의의 3차원 공간상에서도 인체에 미치는 유도전류 해석이 가능한 장접을 갖도록 하 였다. 사례연구로 본 연구에서 제안한 알고리즘을 765 kV급 초고압 송전선로에 적용하여 인체 유도 안전 성을 평가한 결과 765 kV 송전선에서 인체의 단락전류는 인체의 위치에 따라 0.3 mA에서 6.8 mA로 분포 되었다. 특히, 송전선로에서 활선 작업시 단락전류 $I_{sc}$의 크기는 ANSI 허용기준인 5 mA를 념을 수 있어 활 선 작업시 작업자의 전계의 방호 대책을 위해서는 도전물질로 구성된 보호복이 필요함을 알 수 있었다.

• 한국정보통신학회논문지
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• 제11권4호
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• pp.760-765
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• 2007

본 연구에서는 나노구조 이중게이트 FinFET에 대하여 문턱전압이동 특성 및 드레인유기장벽저하(Drain Induced Barrier Lowering; DIBL)특성을 분석하였다. 분석을 위하여 분석학적 전류모델을 개발하였으며 열방사전류 및 터널링전류를 포함하였다. 열방사전류는 포아슨방정식에 의하여 구한 포텐셜분포 및 맥스월-볼쯔만통계를 이용한 캐리어분포를 이용하여 구하였으며 터널링 전류는 WKB(Wentzel-Kramers-Brillouin)근사를 이용하였다. 이 두 모델은 상호 독립적이므로 각각 전류를 구해 더함으로써 문턱 전압을 구하였다. 본 연구에서 제시한 모델을 이용하여 구한 문턱 전압 이동값이 이차원 시뮬레이션값과 비교되었으며 잘 일치함을 알 수 있었다. 분석 결과 10nm 이하에서 특히 터널링의 영향이 증가하여 문턱전압이동 및 DIBL이 매우 현저하게 나타남을 알 수 있었다. 이러한 단채널현상을 감소시키기 위하여 채널두께 및 게이트산화막의 두께를 가능한한 얇게 제작하여야함을 알았으며 이를 위한 산화공정개발이 중요하다고 사료된다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2005년도 하계학술대회 논문집 Vol.6
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• pp.199-200
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• 2005

In this paper, the electrical characteristics and hot-carrier induced electrical performance degradations of high-voltage LDMOSFET fabricated by the existing CMOS technology were investigated. Different from the low voltage CMOS device, the only specific on-resistance was degraded due to hot-carrier stressing in LDMOS transistor. However, other electrical parameters such as threshold voltage, transconductance, and saturated drain current were not degraded after stressing. The amount of on-resistance degradation of LDMOS transistor that was implanted n-well with $1.0\times10^{13}/cm^2$ was approximately 1.6 times more than that of LDMOS transistor implanted n-well with $1.0\times10^{12}/cm^2$. Similar to low voltage CMOS device, the peak on-resistance degradation in LDMOS device was observed at gate voltage of 2.2V while the drain applied voltage was 50V. It means that the maximum impact ionization at the drain junction occurs at the gate voltage of 2.2V applying the drain voltage of 50V.

• ETRI Journal
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• 제26권3호
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• pp.277-280
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• 2004

The distributions of electric field and induced second-order nonlinearity are analyzed in the periodic poling of optical fibers. A quasi-phase matching efficiency for the induced nonlinearity is calculated in terms of both the electrode separation distance between the applied voltage and generalized electrode width for the periodic poling. Our analysis of the quasi-phase matching efficiency implies that the conversion efficiency can be enhanced through adjusting the separation distance, and the electrode width can be maximized if the electrode width is optimized.

• 전기학회논문지P
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• 제60권3호
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• pp.120-125
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• 2011

When we design the grounding grid, dangerous voltage ANSI/IEEE Std. 80 method has been commonly used in the domestic area. However, the suitability of the ground rules for the design environment available. However, the suitability of the ground rules for the design environment available. In this paper, sticks according to the electrode conductor in combination with the mesh in order to design the ground by the IEEE Std.80 was designed. So in this paper, we examined of IEEE Std. 80 touch voltage method marginal utility and we induced for those problems by comparison between IEEE Std. 80 touch voltage value and simulation experimentation value. Furthermore, this paper presents a new design grounding system method that complements the IEEE Std. 80 method.