• Title/Summary/Keyword: induced gate noise

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Impact of Gate Structure On Hot-carrier-induced Performance Degradation in SOI low noise Amplifier (SOI LAN에서 게이트구조가 핫캐리어에 의한 성능저하에 미치는 영향)

  • Ohm, Woo-Yong;Lee, Byong-Jin
    • 전자공학회논문지 IE
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    • v.47 no.1
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    • pp.1-5
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    • 2010
  • This paper presents new results of the impact of gate structure on hot-carrier-induced performance degradation in SOI low noise amplifier. Circuit simulations were carried out using the measured S-parameters of H--gate and T-gate SOI MOSFETs and Agilent's Advanced Design System (ADS) to compare the performance of H-gate LNA and T-gate LNA before and after stress. We will discuss the figure of merit for the characterization of low noise amplifier in terms of impedance matching (S11), noise figure, and gain as well as the relation between device degradation and performance degradation of LNA.

Analytical Thermal Noise Model of Deep-submicron MOSFETs

  • Shin, Hyung-Cheol;Kim, Se-Young;Jeon, Jong-Wook
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.6 no.3
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    • pp.206-209
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    • 2006
  • This paper presents an analytical noise model for the drain thermal noise, the induced gate noise, and their correlation coefficient in deep-submicron MOSFETs, which is valid in both linear region and saturation region. The impedance field method was used to calculate the external drain thermal noise current. The effect of channel length modulation was included in the analytical equation. The noise behavior of MOSFETs with decreasing channel length was successfully predicted from our model.

A Subthreshold Slope and Low-frequency Noise Characteristics in Charge Trap Flash Memories with Gate-All-Around and Planar Structure

  • Lee, Myoung-Sun;Joe, Sung-Min;Yun, Jang-Gn;Shin, Hyung-Cheol;Park, Byung-Gook;Park, Sang-Sik;Lee, Jong-Ho
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.12 no.3
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    • pp.360-369
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    • 2012
  • The causes of showing different subthreshold slopes (SS) in programmed and erased states for two different charge trap flash (CTF) memory devices, SONOS type flash memory with gate-all-around (GAA) structure and TANOS type NAND flash memory with planar structure were investigated. To analyze the difference in SSs, TCAD simulation and low-frequency noise (LFN) measurement were fulfilled. The device simulation was performed to compare SSs considering the gate electric field effect to the channel and to check the localized trapped charge distribution effect in nitride layer while the comparison of noise power spectrum was carried out to inspect the generation of interface traps ($N_{IT}$). When each cell in the measured two memory devices is erased, the normalized LFN power is increased by one order of magnitude, which is attributed to the generation of $N_{IT}$ originated by the movement of hydrogen species ($h^*$) from the interface. As a result, the SS is degraded for the GAA SONOS memory device when erased where the $N_{IT}$ generation is a prominent factor. However, the TANOS memory cell is relatively immune to the SS degradation effect induced by the generated $N_{IT}$.

Reliability Analysis of SiGe pMOSFETs Formed on PD-SOI (PD-SOI기판에 제작된 SiGe p-MOSFET의 신뢰성 분석)

  • Choi, Sang-Sik;Choi, A-Ram;Kim, Jae-Yeon;Yang, Jeon-Wook;Han, Tae-Hyun;Cho, Deok-Ho;Hwang, Young-Woo;Shim, Kyu-Hwan
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2007.06a
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    • pp.533-533
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    • 2007
  • The stress effect of SiGe p-type metal oxide semiconductors field effect transistors(MOSFETs) has been investigated to compare device properties using Si bulk and partially depleted silicon on insulator(PD SOI). The electrical properties in SiGe PD SOI presented enhancements in subthreshold slope and drain induced barrier lowering in comparison to SiGe bulk. The reliability of gate oxides on bulk Si and PD SOI has been evaluated using constant voltage stressing to investigate their breakdown (~ 8.5 V) characteristics. Gate leakage was monitored as a function of voltage stressing time to understand the breakdown phenomena for both structures. Stress induced leakage currents are obtained from I-V measurements at specified stress intervals. The 1/f noise was observed to follow the typical $1/f^{\gamma}$ (${\gamma}\;=\;1$) in SiGe bulk devices, but the abnormal behavior ${\gamma}\;=\;2$ in SiGe PD SOI. The difference of noise frequency exponent is mainly attributed to traps at silicon oxide interfaces. We will discuss stress induced instability in conjunction with the 1/f noise characteristics in detail.

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Simulative Investigation of Spectral Amplitude Coding Based OCDMA System Using Quantum Logic Gate Code with NAND and Direct Detection Techniques

  • Sharma, Teena;Maddila, Ravi Kumar;Aljunid, Syed Alwee
    • Current Optics and Photonics
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    • v.3 no.6
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    • pp.531-540
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    • 2019
  • Spectral Amplitude Coding Optical Code Division Multiple Access (SAC OCDMA) is an advanced technique in asynchronous environments. This paper proposes design and implementation of a novel quantum logic gate (QLG) code, with code construction algorithm generated without following any code mapping procedures for SAC system. The proposed code has a unitary matrices property with maximum overlap of one chip for various clients and no overlaps in spectra for the rest of the subscribers. Results indicate that a single algorithm produces the same length increment for codes with weight greater than two and follows the same signal to noise ratio (SNR) and bit error rate (BER) calculations for a higher number of users. This paper further examines the performance of a QLG code based SAC-OCDMA system with NAND and direct detection techniques. BER analysis was carried out for the proposed code and results were compared with existing MDW, RD and GMP codes. We demonstrate that the QLG code based system performs better in terms of cardinality, which is followed by improved BER. Numerical analysis reveals that for error free transmission (10-9), the suggested code supports approximately 170 users with code weight 4. Our results also conclude that the proposed code provides improvement in the code construction, cross-correlation and minimization of noises.

An MMIC VCO Design and Fabrication for PCS Applications

  • Kim, Young-Gi;Park, Jin-Ho
    • Journal of Electrical Engineering and information Science
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    • v.2 no.6
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    • pp.202-207
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    • 1997
  • Design and fabrication issues for an L-band GaAs Monolithic Microwave Integrated Circuit(MMIC) Voltage Controlled Oscillator(VCO) as a component of Personal Communications Systems(PCS) Radio Frequency(RF) transceiver are discussed. An ion-implanted GaAs MESFET tailored toward low current and low noise with 0.5mm gate length and 300mm gate width has been used as an active device, while an FET with the drain shorted to the source has been used as the voltage variable capacitor. The principal design was based on a self-biased FET with capacitive feedback. A tuning range of 140MHz and 58MHz has been obtained by 3V change for a 600mm and a 300mm devices, respectively. The oscillator output power was 6.5dBm wth 14mA DC current supply at 3.6V. The phase noise without any buffer or PLL was 93dB/1Hz at 100KHz offset. Harmonic balance analysis was used for the non-linear simulation after a linear simulation. All layout induced parasitics were incorporated into the simulation with EEFET2 non-linear FET model. The fabricated circuits were measured using a coplanar-type probe for bare chips and test jigs with ceramic packages.

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Analysis on the Noise Factors of Static Induction Photo-Transistor (SIPT) (1) - The SIPT's Equivalent Circuits for the Analysis on the Noise Factors - (정전유도(靜電誘導) 포토 트랜지스터의 잡음(雜音) 원인(原因) 분석(分析) (1) - 잡음(雜音) 원인(原因) 분석(分析)을 위한 SIPT 등가회로(等價回路) -)

  • Kim, Jong-Hwa
    • Journal of Sensor Science and Technology
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    • v.4 no.4
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    • pp.29-40
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    • 1995
  • In this paper, the noise equivalent cicuits that is necessary to the formulation of D.C. and noise characteristics, residual component and input capacitance so as to analyze on the noise factors of the SIT is proposed. The simplest noise equivalent circuit is the model representing the mechanism of the SIT and the measured values in this model were found as small as the values of the shot-noise. In the source resistance inserted equivalent circuit is conformed that the shot-noise will be reduced by the negative-feedback effect of the source resistance. In oder to analyze the correct noise reduction factor, I proposed the equivalent circuit which the formulas of the source and drain resistance was induced. In the experiment which affirm the equivalent circuits, the influence of the signal source resistance and output load resistance on the residual component is small and the residual component can be expressed by the equivalent input noise resistance. Moreover, the input capacitance is 13.6 pF when the load resistance is $0{\Omega}$ and the capacitance which does not concern with the SIT operation directly, that is, gate wire etc, is 10pF or so.

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Study of Shock Tube for Wave Phenomenon in High Speed Railway Tunnel(1) - On the characteristics of Compression Wave - (고속철도 터널에서 발생하는 파동현상에 관한 충격파관의 연구(1) - 압축파의 특성에 대하여 -)

  • ;松尾一泰
    • Transactions of the Korean Society of Mechanical Engineers
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    • v.18 no.10
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    • pp.2686-2697
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    • 1994
  • When a railway train enters a tunnel at high speed, a compression wave is formed in front of the train and propagates along the tunnel. The compression wave subsequently emerges from the exit of the tunnel, which causes an impulsive noise. In order to estimate the magnitudes of the noises and to effectively minimize them, the characteristics of the compression wave propagating in a tunnel must be understood. In the present paper, the experimental and analytical investigations on the attenuation and distortion of the propagating compression waves were carried out using a model tunnel. This facility is a kind of open-ended shock tube with a fast-opening gate valve instead of a general diaphragm. One-dimensional flow model employed in the present study could appropriately predict the strength of the compression wave, Mach number and flow velocity induced by the compression wave. The experimental results show that the strength of a compression wave decreases with the distance from the tunnel entrance. The decreasing rate of the wave strength and pressure gradient in the wave is strongly dependent on the strength of the initial compression wave at the tunnel entrance.

Design and Implementation of Digital Electrical Impedance Tomography System (디지털 임피던스 영상 시스템의 설계 및 구현)

  • 오동인;백상민;이재상;우응제
    • Journal of Biomedical Engineering Research
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    • v.25 no.4
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    • pp.269-275
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    • 2004
  • Different biological tissues have different values of electrical resistivity. In EIT (electrical impedance tomography), we try to provide cross-sectional images of a resistivity distribution inside an electrically conducting subject such as the human body mainly for functional imaging. However, it is well known that the image reconstruction problem in EIT is ill-posed and the quality of a reconstructed image highly depends on the measurement error. This requires us to develop a high-performance EIT system. In this paper, we describe the development of a 16-channel digital EIT system including a single constant current source, 16 voltmeters, main controller, and PC. The system was designed and implemented using the FPGA-based digital technology. The current source injects 50KHz sinusoidal current with the THD (total harmonic distortion) of 0.0029% and amplitude stability of 0.022%. The single current source and switching circuit reduce the measurement error associated with imperfect matching of multiple current sources at the expense of a reduced data acquisition time. The digital voltmeter measuring the induced boundary voltage consists of a differential amplifier, ADC, and FPGA (field programmable gate array). The digital phase-sensitive demodulation technique was implemented in the voltmeter to maximize the SNR (signal-to-noise ratio). Experimental results of 16-channel digital voltmeters showed the SNR of 90dB. We used the developed EIT system to reconstruct resistivity images of a saline phantom containing banana objects. Based on the results, we suggest future improvements for a 64-channel muff-frequency EIT system for three-dimensional dynamic imaging of bio-impedance distributions inside the human body.

Ethanol inhibits Kv7.2/7.3 channel open probability by reducing the PI(4,5)P2 sensitivity of Kv7.2 subunit

  • Kim, Kwon-Woo;Suh, Byung-Chang
    • BMB Reports
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    • v.54 no.6
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    • pp.311-316
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    • 2021
  • Ethanol often causes critical health problems by altering the neuronal activities of the central and peripheral nerve systems. One of the cellular targets of ethanol is the plasma membrane proteins including ion channels and receptors. Recently, we reported that ethanol elevates membrane excitability in sympathetic neurons by inhibiting Kv7.2/7.3 channels in a cell type-specific manner. Even though our studies revealed that the inhibitory effects of ethanol on the Kv7.2/7.3 channel was diminished by the increase of plasma membrane phosphatidylinositol 4,5-bisphosphate (PI(4,5)P2), the molecular mechanism of ethanol on Kv7.2/7.3 channel inhibition remains unclear. By investigating the kinetics of Kv7.2/7.3 current in high K+ solution, we found that ethanol inhibited Kv7.2/7.3 channels through a mechanism distinct from that of tetraethylammonium (TEA) which enters into the pore and blocks the gate of the channels. Using a non-stationary noise analysis (NSNA), we demonstrated that the inhibitory effect of ethanol is the result of reduction of open probability (PO) of the Kv7.2/7.3 channel, but not of a single channel current (i) or channel number (N). Finally, ethanol selectively facilitated the kinetics of Kv7.2 current suppression by voltage-sensing phosphatase (VSP)-induced PI(4,5)P2 depletion, while it slowed down Kv7.2 current recovery from the VSP-induced inhibition. Together our results suggest that ethanol regulates neuronal activity through the reduction of open probability and PI(4,5)P2 sensitivity of Kv7.2/7.3 channels.